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In this paper we describe a flexible infrastructure that can directly interface unmodified application executables with FPGA hardware acceleration IP in order to 1), facilitate faster computer architecture simulation, and 2), to prototype microarchitecture or accelerator IP. Dynamic binary modification tool plugins are directly interfaced to the application under evaluation via flexible software interfaces...
This paper subsumes the concept of Internet of Things on a Tera Hertz RAM on the 40nm FPGA. Time analysis has been performed on a Tera Hertz RAM. This produces correspondingly higher speeds as compared to any other form of RAM available. The main focus has been on studying the slack for various frequencies. Slack is a kind of error and should be as low as possible. We aim to find that optimum condition...
Nowadays, the release of SoC products has come to a burst. Time-to-market of these products has been shortened to an extreme, nearly 8 to 12 months. To reduce production period, hardware architects generally combine well-tuned IP cores in their designs. To guarantee the process of SoC software development, which will finally decide the release time of products, a fast prototyping simulation platform...
At present, the multilevel FPGA scheme is used widely in system for people life. In order to satisfy the need of product update, it is very urgent to find a way to solve the problem of Multilevel FPGA upgrade. The traditional method of single FPGA upgrade contains two steps, the first one is storing the configuration file to external NOR_FLASH; the second step is reading the file from external NOR_FLASH...
The Super KEKB factory project at KEK in Japan with the ultimate goal of integrated luminosity of 50 ab-1 has been prepared to study the Beyond Standard Model physics from B meson and tau/charm weak decays. A online trigger system is indispensable to suppress a mount of beam background events from high beam currents of electron and positron and to enhance physics oriented events. Two kind of Level-1...
A smart camera processor has to perform substantial amount of processing of data-intensive operations. Hence, it is vital to identify critical segments of the processing load by involving HW/SW codesign in smart camera system design. This paper presents a novel fully automatic hybrid framework that combines heuristic and knowledge-based approaches to partition, allocate and schedule IP modules efficiently...
We propose in this paper, a timing analysis of dynamic partial reconfiguration (PR) applied to a NoC (network on chip) structure inside a FPGA. In the context of a SDR (software defined radio) example, PR is used to dynamically reconfigure a baseband processing block of a 4G telecommunication chain running in real-time (data rates up to 100 Mbps). The results presented show the validity of our methodology...
Universal bus interface is very helpful for improving the popularity of the device or equipment on both SoC integration and board level computing system design. Because of the diversity of bus interface accessing protocol, universality is usually unable to be achieved in a common interface design. Through introducing the concept of sequence configuration, a method of designing universal bus interface...
The paper describes an original design of IEEE1149.1 testing bus controller IP core using reusable technology. We have designed the structure of IP core according to the function of IEEE1149.1 testing bus controller. Every function module of IP core was explained detailedly in this paper, including interface of microprocessor module, command control module, TMS creation module, TCK creation module...
Evolving combinational and sequential logic circuit is still under investigation within the evolvable hardware community. This situation is somewhat surprising since the electronic design automation industry is mature and the tools in wide use today are incredibly powerful. It therefore makes sense to see how well evolvable hardware techniques compare against the existing design methods. That comparison...
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