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The Kiwi project revolves around a compiler that converts C# .NET bytecode into Verilog RTL and/or SystemC. An alpha version of the Kiwi toolchain is now open source and a user community is growing. We will demonstrate an incremental approach to large system assembly of HLS and blackbox components, based on an extended IP-XACT intermediate representation. We show how to address multi-FPGA designs...
The architecture of the Microsoft Catapult II cloud places the accelerator (FPGA) as a bump-in-the-wire on the way to the network and thus promises a dramatic reduction in latency as layers of hardware and software are avoided. We demonstrate this capability with an implementation of the 3D FFT. Next we examine phased application elasticity, i.e., the use of a reduced set of nodes for some phases...
In this paper, an FPGA-based implementation of Frequent Items Counting is proposed. The architecture deploys the equality comparator matrix for comparing the input items with themselves to count them instantly within a single operating clock. The proposed architecture is applied to the case of the 8-bit item. That means 256 different types of items in total. The system is built and verified on the...
Field Programmable Gate Array (FPGAs) have been known as high efficient devices providing architectural flexibility, reconfigurability and high timing performances for embedded real time systems. For highly critical applications, FPGA provides low power consumption, significant resource optimization and can meet the real time constraints. Data acquisition systems and many measurement systems for industrial...
Speed-Up Robust Feature (SURF) is an effective algorithm for feature extraction. We propose a novel Scaled-RAM Interpolator (SRI) on FPGA to deal with the high complexity of SURF by introducing two methods. 1) Interpolation of Integral Image (I3) restores the sub-pixel details of image to improve matching precision, and halves the memory access to achieve acceleration; 2) Multi-Scaled RAM (MSR) normalizes...
This paper presents an FPGA based miniature, multi-functional signal generator with digital controller inside to adapt applications such as wireless sensor network (WSN) and software define radio (SDR) system. To reduce design complexity and decrease development time, this work adopts a novel SOPC design methodology, which means using embedded soft-core microprocessor Nios II and EDA tool Quartus...
FPGA capacity has grown rapidly and emerging large applications comprise a large number of hard and soft modules. The communication among these modules requires high demand from fabric interconnect, causing routing congestion and performance degradation. This problem will be more pronounced with process scaling since the technology is not improving wire resistance. A general technique to reduce interconnect...
Pulse compression is an important signal processing technique in radar system. Based on field programmable gate array (FPGA), an improved method for implementing pulse compression is proposed to reduce the resource usage. As the FFT and IFFT transform are the main calculations of the pulse compression and take up many resources, single FFT IP core is used to realize two operations in the improved...
This paper subsumes the concept of Internet of Things on a Tera Hertz RAM on the 40nm FPGA. Time analysis has been performed on a Tera Hertz RAM. This produces correspondingly higher speeds as compared to any other form of RAM available. The main focus has been on studying the slack for various frequencies. Slack is a kind of error and should be as low as possible. We aim to find that optimum condition...
A new control scheme for eliminating garbage collection during high-speed analysis of big-graph data stored in NAND flash memory is proposed and evaluated. During big-graph analysis, intermediate results of the analysis stored in NAND flash memory are updated repeatedly. When a conventional control scheme is applied, excessive data copying, called “garbage collection,” occurs because overwriting data...
Packet classification is a network kernel function that has been widely researched over the past decade. However, most previous work has only focused on achieving high-throughput without considering its energy-efficiency implications. With the rapid growth of Internet, energy-efficiency has become an important metric for networks. We present the design of an energy-efficient packet classifier on Field-Programmable...
In this paper we present TNT10G (multi-Terabyte trace Network Tester), an FPGA-based tool for replaying and capturing massive Ethernet traces at 10 Gb/s. The tool is capable of reproducing and storing terabytes of network traffic at line rate, even if small packets are being used. Moreover, since the design works at low level (XGMII), accuracy is better than 10 ns, and it is also possible to observe...
This paper describes an efficient hardware implementation of a cross-correlation algorithm on a Field-Programmable Gate Array (FPGA) platform with the purpose of visually identifying coins. This method has the ability to compare images obtained via a video camera with those stored in memory, thereby, accepting/rejecting coins-under-test at the very high-speed demanded by today's coin validation mechanisms...
The 3D FFT is critical in many physical simulations and image processing applications. On FPGAs, however, the 3D FFT was thought to be inefficient relative to other methods such as convolution-based implementations of multigrid. We find the opposite: a simple design, operating at a conservative frequency, takes 4Μs for 163, 21Μs for 323, and 215Μs for 643...
Named Data Networking (NDN) is an emerging future Internet architecture with an alternative communication paradigm. For NDN, name lookup, just like IP address lookup for TCP/IP, plays an important role in forwarding. However, performing Longest Prefix Matching (LPM) to NDN names is more challenging. Recently, Graphic Processing Units (GPUs) have been shown to be of value in supporting wire speed name...
The 3D FFT is critical in electrostatics computations such as those used in Molecular Dynamics simulations. On FPGAs, however, the 3D FFT was thought to be inefficient relative to other methods such as convolution-based implementations of multigrid. We find the opposite: a simple design using less than half the chip resources, and operating at a very conservative frequency, takes less than 50us for...
For the achievement of LFM signal acquisition, pulse compression and storage, the hardware platform is built. A way to implement the pulse compression of the LFM signal based on FPGA is presented. This paper describes in detail the functions and implementation methods of the various functional modules of the FPGA in the pulse compression process. A theoretical simulation on the pulse compression is...
We propose a unified methodology for optimizing IPv4 and IPv6 lookup engines based on the balanced range tree (BRTree) architecture on FPGA. A general BRTree-based IP lookup solution features one or more linear pipelines with a large and complex design space. To allow fast exploration of the design space, we develop a concise set of performance models to characterize the tradeoffs among throughput,...
Heterogeneous multicore platform has been widely used in various areas to achieve both power efficiency and high performance. This paper proposes a FPGA implementation of a hardware scheduler supporting parallel dataflow execution on heterogeneous multicore platform. The scheduler has the capability to explore potential parallelism, leading to a high acceleration of dependence-aware applications....
This paper studies a new approach for board-level test based on synthesizable embedded instruments implementted on FPGA. This very recent methodology utilizes programmable logic devices (FPGA) that are usually available on modern PCBs to a large extent. The purpose of an embedded instrument is to carry out a vast portion of test application related procedures, perform measurement and configuration...
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