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MPI is the traditional paradigm to parallelize applications for High Performance Computing environments. AzequiaMPI is an implementation of the MPI-1.3 standard. Its thread-based architecture enables it to run on high-end HPC machines as well as on embedded environments as soft-core processor in FPGAs. This article describes the experience of building a maintainable cluster of fourteen popular Xilinx...
We report on a Synchronous Ethernet based clock distribution and timestamp synchronization implementation over 1000BASE-T (Gigabit over twisted pair) Ethernet. A central 125 MHz global clock is distributed to all detector modules using only commercial off-the-shelf components. The timestamps generated on different modules has a maximum fixed offset of 24-60 ns (depending on the switch tested), and...
MEMOCODE Design Contest challenged teams to implement the architecture for a unique type of Deep Packet Inspector called CANSCID. This paper describes this unique problem statement, and the motivation for choosing it. This paper is followed by short descriptions prepared by individual teams detailing their particular approach to solving the problem.
As FPGAs become larger and more powerful, they are increasingly used as accelerator devices for compute-intensive functions. Input/Output (I/O) speeds can become a bottleneck and directly affect the performance of a reconfigurable accelerator since the chip will idle when there are no data available. While PCI Express represents the currently fastest and most expensive solution to connect a FPGA to...
This paper introduces a SOPC high-speed interconnection platform based on FPGA convenient for integrate processing system with Ethernet. Embedded processor PowerPC405e, corporated with logic array, implement seamless connection with processing system, as well as gigabit Ethernet. It shows flexibility and efficiency through data storage and playback with NAS storage system.
More fundamental than IP lookups and packet classification in routers is the extraction of fields such as IP Dest and TCP Ports that determine packet forwarding. While parsing of packet fields used to be easy, new shim layers (e.g., MPLS, 802.1Q, MAC-in-MAC) of possibly variable length have greatly increased the worst-case path in the parse tree. The problem is exacerbated by the need to accommodate...
Ethernet based network protocol replaces fieldbus systems due to its high speed, safety, and extendibility. At the system level, use of an additional network requires effort to implement the new environment. The user has to analyze and organize two networks. This paper proposes FPGA based network controller between Ethernet and EtherCAT. It does not incur additional cost and effort. As it is based...
This paper describes an implementation in hardware of Internet Protocol version 4. Routing and addressing features were integrated with Network Interfaces and synthesized to a Stratix II FPGA device. Our work showed two implementations of a full duplex Internet Protocol version 4. The first implementation consists in a Reference design and the second uses the same design but with more buffer space...
This paper presents a proposal of a Gigabit UDP/IP network stack in FPGA, which is the stack of the widely used in VoIP and Video-conference applications. This network node implements the Network, Transport and Link Layer of a traditional stack. This architecture is integrated and developed using Xilinx ISE tool and synthesized to a Spartan-3E FPGA. We show architecture details, timing and area results...
Recent trends show an increasing number of weblabs, implemented at universities and schools, supporting practical training in technical courses and providing the ability to remotely conduct experiments. However, their implementation is typically based on individual architectures, unable of being reconfigured with different instruments/modules usually required by every experiment. In this paper, we...
This paper describes the design of a virtualized application and networking infrastructure (VANI) node that can be used to facilitate network architecture experimentation. Currently the VANI nodes provide four classes of physical resources: processing, reconfigurable hardware, storage and interconnection fabric, but the set of sharable resources can be expanded. Virtualization software allows slices...
We present a dynamic computing platform that allows for rapid prototyping of image and video processing applications systems. Here, an Ethernet MAC is used to stream video in and out of the FPGA. The output video is also sent to a video port for display. The system features a simple way to specify the dynamic video processing modules that are going to be multiplexed in time. The dynamic control is...
The dynamic reconfiguration technique based on FPGA (field-programmable gate array) can improve the resource utilization. The dynamic reconfiguration principles and methods are discussed. A remote dynamic reconfiguration scheme using Xilinx Virtex-II FPGA and SMCS Ethernet PHY (physical layer transceiver) is proposed. The hardware of system is designed with Xilinx Virtex-IIXC2V30P FPGA that embeds...
Network fragmentation is the process of splitting a large amount of communication data into smaller fragments that comply with the Maximum Transmission Unit supported by the interconnect. We present a novel fragmentation approach which optimises communication fragmentation based on the amount of data remaining to be exchanged. Our fragmentation approach has up to 30% lower latency when exchanging...
The development of a new tri-modality preclinical Computed Tomography apparatus (??CT), Single Photon Emission Computed Tomography apparatus (??SPECT) and Positron Emission Tomography apparatus (??PET) dedicated to small animal imaging tomography is underway in the group ImaBIO at the Institut Pluridisciplinaire Hubert Curien. The ??CT and ??SPECT scanners are working quite fine and now used by biologists...
We report on a distributed online coincidence detection implementation that we have recently added to the miniPET-II small animal PET scanner. The implementation uses standard Ethernet and IP multicasting techniques, therefore no architectural changes were necessary to the existing system. For 2D reconstruction the implementation scales with the number of detectors in the system, so it can be used...
An Internet configurable distributed domotic network is presented. The network nodes are implemented with field programmable logic devices (FPGA). Each of them contains two modules, one for receiving field sensors activity signals and controlling devices responsible to modify the environment, and the other an ETHERNET compatible dedicated communication module. Simulation and implementation over SPARTAN...
The communication manager module embedded in a dedicated system configurable via Internet design description and XILINX Spartan 3 FPGA implementation are presented. Keeping Internet connectivity as a priority, minimum subsets of IEEE 802.3 standard rules for Ethernet data interchange and RFC826 and RFC791 recommendations for address resolution protocol (ARP) and Internet protocol (IP) respectively,...
A hardware structure of LXI bus instruments based on Nios II core is presented in this paper. By the translation of muC/OS II operating system and the lwIP stack on the Nios II core, the TCP and IP protocols are realized. The Web server and the Ethernet protocols are also realized by the programming interface supplied by the lwIP stack. Finally the paper tests the network protocols on the LXI module...
Providing flexible satellite communications through frequency- and waveform-agile onboard processing is an emerging trend for missions such as the Air Force's Operationally Responsive Space (ORS). Data packet routing features that seek to improve network flexibility and performance by going beyond traditional ldquobent piperdquo platforms are being leveraged to meet the objectives of ORS. The Programmable...
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