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Neuromorphic systems have been increasing in size and complexity in recent years, thanks also the adoption of the Address-Event Representation (AER) as a standard for transmitting signals among chips, and building multi-chip event-based systems. AER mapper devices that route Address-Events from multiple sources to different multiple destinations are crucial components of these systems, as they allow...
Nowadays, computers are indispensable tools for most of everyday activities ranging from consumer electronics to industrial process automation. Complexity of new applications leads computer engineers to use embedded systems in order to develop high performance technological solutions that can achieve high speed processing while exploiting hardware resources efficiently. In order to develop embedded...
A new method is proposed for a ground telecontrol/telemetry terminal processor design. The design is based on ATmega1280 + FPGA structure, and data exchange is realized through multiple external interruptions between ATmega1280 and FPGA. It elaborately gives the terminal's system composition; external RAM R/W, external interrupt, A/D converter, timer and serial interrupt routine design in ATmega1280...
This paper introduces a high speed data acquisition system based on NIOS II, especially focuses on the development process of NIOS II soft-core in data acquisition system. Acquisition data is transferred to computer for displaying and analysising by USB interface. Acquisition rate is 250MSPS, the real-time and low-pass filter is used as well, the acquisition data is stored in the RAM first, then processed...
In the field of microprocessors, speeds of processor doubles in every 18 months as, new microprocessors are always being designed using more and more advanced features. So, it's always a challenge to design a new microprocessor with faster execution speed. In this paper microarchitecture of superscalar processor is to be designed using VLSI. This Proposed design is based on the rigorous research done...
Nowadays, there is an increasingly recognized need for more computing power, which has led to multicore processors. However, this evolution is still restrained by the poor efficiency of memory chips. As a possible solution to the problem, this paper examines a model of re-distributing the memory resources assigned to the processor, especially the on-chip memory, in order to achieve higher performance...
This paper describes implementation of Web server using Altera Nios II embedded IP core, a configurable general purpose embedded RISC processor with embedded peripheral architecture. A Web server is a computer that delivers Web pages to other computers in the network. Every Web server has a unique IP address and possibly a domain name. Any computer can work as Web server by installing server software...
In order to make Space Information Processing System (SIPS) based on Commercial-Off-The-Shelf (COTS) have a much stronger ability of radiation resistance in space, this paper presents multilevel fault-tolerant technique based on FPGA and Single Event Latch-up (SEL) resistance protection circuit. The multilevel fault-tolerant technique includes the dual fault-tolerant design on system level, the redundancy...
Embedded systems became more and more pervasive in our world, whereas the security problem severely influence its credibility. This paper presented a security solution for embedded systems, which is called TFSES (security embedded systems base on TCM and FPGA). In this solution, a security FPGA checked the integrity of instructions and data in flash chip before running of the embedded processor. The...
This paper introduces a new way-prediction scheme for achieving low energy consumption and high performance for set-associative instruction cache. The proposed scheme is based on the different cases of how program execution proceeds. By predicting for the sequential instruction flow and non-sequential one respectively, we can achieve a high way prediction hit rate. Since way-prediction doesnpsilat...
DRAM is an essential memory of a modern computer. Microprocessor loads the data which the user requested into DRAM before processing the data. Hence, DRAM contains important information in a computer. Recently, security researchers disclosed that DRAM is vulnerable to attack. Through Cold Boot Attack, DRAM contents can be recovered even after the computer has been powered off for several minutes....
To prevent electronic products being copied illegally, based on CPLD/FPGA, a new method with the highest security anti-piracy by adopting AT88SC0104C is presented in this paper. The design adopts not only Verilog HDL but also VHDL language programming to fulfill the complete authentication process of AT88SC0104C in CPLD/FPGA device. Because the code in CPLD/FPGA can not be disassembled, the possibility...
This paper analyses structure and algorithm of floating-point ALU, and implements multiplication and division operation in the homo-hardware circuit. The floating-point multiplication and division ALU supports floating-point number according with IEEE-754 standard. This ALU adopts 4-level pipelining structure: '0' operation number check, exponent addition and subtraction operation, fraction multiplication...
PicoBlaze is an 8-bit soft core microprocessor developed by Xilinx that can be synthesized in some FPGA families. This paper presents a set of peripherals that have been developed to interface with PicoBlaze: VGA control, serial communication, PS/2 keyboard port and LCD control. To demonstrate its capabilities, the system has been implemented in a FPGA board and some typical control and monitoring...
High-performance reconfigurable computers (HPRCs) are parallel computers but with added FPGA chips. Examples of such systems are the Cray XT5h and Cray XD1, the SRC-7 and SRC-6, and the SGI Altix/RASC. The execution of parallel applications on HPRCs mainly follows the single-program multiple-data (SPMD) model, which is largely the case in traditional high-performance computers (HPCs). In addition,...
This paper introduces architecture and feature of 32-bit micro-processor, and describes internal data path in processor. Through analysis of function and theory of RISC CPU instruction decoder module, we design instruction decoder (ID) module of 32-bit CPU by pipeline theory. The instruction decoder includes register file, write back data to register file, sign bit extend, relativity check, and it...
The purpose of TAFT fault tolerance studies conducted at CNES is to prepare the space community for the significant evolution linked to the usage of COTS components for developing spacecraft supercomputers. CNES has patented the DMT and DT2 fault-tolerant architectures with 'light' features. The development of a DMT/DT2 testbench based on a PowerPC7448 microprocessor from e2v is presented in this...
The traditional numerical control system is independent and close. Different manufacturers are not compatible with each other which lead to much time and resources waste. A small reconfigurable numerical control machining center based on embedded microprocessor S3C2410 is implemented in the paper. Each module in the system is connected by standard interfaces which make it easy to reconstruct or expand...
The Falcon emulated-digital CNN-UM (cellular neural/nonlinear networks universal machine) architecture has been extended by an embedded GAPU (global analogic programming unit) using the flexible Xilinx MicroBlaze soft-core processor to take full advantage of the joint computing power of high-speed distributed arithmetics and programmability. The implemented GAPU provides a stand-alone operation, which...
Polymorphous computing systems have been introduced in multi-core/tile architectures as a result of the DARPA Polymorphous Computing Architectures (PCA) program. We will review the state-of-the-art in multi-core systems, first by reviewing the PCA developed systems, and secondly by reviewing recently announced multi-core chips. The PCA-developed USC-ISI/Raytheon/Mercury MONARCH chip in addition to...
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