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This paper designs a Flash controller, which helps the FPGA main state-machine to manage a Flash memory chip efficiently. The controller builds its own instruction set. User operates the proposed controller with the system clock of FPGA without caring about the timing sequences required by the Flash. The proposed Flash controller develops its own method for the reorganization and mapping of invalid...
A new method is proposed for a ground telecontrol/telemetry terminal processor design. The design is based on ATmega1280 + FPGA structure, and data exchange is realized through multiple external interruptions between ATmega1280 and FPGA. It elaborately gives the terminal's system composition; external RAM R/W, external interrupt, A/D converter, timer and serial interrupt routine design in ATmega1280...
With the growing needs for advanced functionalities in modern embedded systems, it is now necessary to integrate multiple processors in the system, preferably on a single chip, to support the required computing complexity. The problem is that such multiprocessor system-on-chip (MPSoC) architecture is very complex and its internal behavior is very difficult to track. An effective tool for profiling...
This paper describes implementation of Web server using Altera Nios II embedded IP core, a configurable general purpose embedded RISC processor with embedded peripheral architecture. A Web server is a computer that delivers Web pages to other computers in the network. Every Web server has a unique IP address and possibly a domain name. Any computer can work as Web server by installing server software...
We describe a residue number system (RNS) implementation of the 192-bit elliptic curve digital signature algorithm over GF(p). It uses a Tensilica Xtensa LX2.1 microprocessor core with hardware extensions to improve the performance of RNS operations. The low power and small area of the enhanced Xtensa LX2.1 core make it suitable for smart cards. This implementation is the first to use the RNS for...
Multiprocessor system-on-chip design (MPSoC) is becoming a regular feature of the embedded systems. Shared-bus systems hold many advantages, but they do not scale. Network on chip (NoC) offers a promising solution to the scalability problem by enhancing the topology design. However, standard NoCs are only scalable within a chip. To be able to build infinitely scalable structures, a method to enhance...
This paper proposed a method of the local learning for S_CMAC_GBF. CMAC_GBF performs better than CMAC in the learning convergence speed and accuracy. The advantages of S_CMAC_GBF are simpler addressing structure, lower consuming memory space and easier hardware application, and it will not degrade the accuracy of the original input. For achieving better learning efficiency and speeding the hardware...
For the secure transaction of data between the central processing unit (CPU) of a satellite on board-computer and its local random access memory (RAM), the program memory has been usually designed with triple modular redundancy (TMR), which is a hardware implementation that includes replicated memory circuits and voting logic to detect and correct a faulty value. TMR error correction technique allows...
This paper presents prototype board and its operating system dedicated for application specific parallel processing. The proposed architecture consists of two AVR microprocessors, FPGA Spartan3, SRAM and flash EEPROM memories, DA converters, and several serial communication ports. To make the system "designer friendly" a supervising algorithm, which can be called as a kind of "operating...
Clouds have a critical role in many studies, e.g. weather- and climate-related studies. However, they represent a source of errors in many applications, and the presence of cloud contamination can hinder the use of satellite data. This requires a cloud detection process to mask out cloudy pixels from further processing. The trend for remote sensing satellite missions has always been towards smaller...
Encouraged by continuous advances in FPGA technologies, we explore high performance multi-processor-on-a-programmable-chip (MPoPC) reconfigurable architectures. This paper proposes a methodology for assigning resources at run time and scheduling large scale floating point, data parallel applications on our mixed mode HERA MPoPC. HERA stands for heterogeneous reconfigurable architecture. An application...
This paper introduces a language and framework for designing multiprocessor architectures in the logic programming domain. Our goal is to enable application developers in areas such as machine learning and cognitive robotics to produce high-performance designs without detailed knowledge of hardware development. This framework provides a high level of abstraction, enabling rapid system generation and...
Implementation of a real-time image visualization system on a reconfigurable chip (FPGA) is proposed. The system utilizes an innovative stereoscopic image capture, processing and visualization technique. Implementation is done as a two stage process. In the first stage, the stereo pair is captured using two image sensors. The captured images are then synchronized and sent to the second stage for fusion...
This paper presents a new architecture of scaleable FFT processor using hardware/software codesign technique for orthogonal frequency division multiplexing (OFDM) systems. The architecture uses a radix-4 butterfly node located on both hardware and software processing elements. We employ an in-place memory strategy, resulting that the butterfly inputs and outputs can be stored at the same memory location...
SRAM FPGAs are vulnerable to security breaches such as bitstream cloning, reverse-engineering, and tampering. Bitstream encryption and authentication are two most effective and practical solutions to improve the security of FPGAs. In this paper, we investigate a method to perform a secure dynamic partial reconfiguration of SRAM FPGAs using embedded processor cores. Two schemes based on hard-wired...
This paper describes a novel hardware accelerator for Monte Carlo (MC) simulation, and illustrates its implementation in field programmable gate array (FPGA) technology for speeding up financial applications. Our accelerator is based on a generic architecture, which combines speed and flexibility by integrating a pipelined MC core with an on-chip instruction processor. We develop a generic number...
This paper deals with the implementation of globally asynchronous locally synchronous (GALS), micropipelined processor in field programmable gate arrays (FPGA). Associated issues like delay model incorporating on-chip, technology independent single inverter ring oscillator (SIRO) and an unbundled datapath based on bit-encoding and return-to-zero (RTZ) schemes are also presented. Post-layout simulation...
In this paper, a vector unit tightly coupled with a five-stage pipelined scalar processor is designed and implemented on an FPGA platform. This system supports IEEE 754 single-precision floating-point calculations and sparse matrix operations. The W-matrix linear equation solution method for sparse systems is run on this vector processor. The obtained performance demonstrates that large linear algebraic...
Optically reconfigurable gate arrays (ORGAs) have been developed to allow rapid reconfiguration. We have developed an optically differential reconfigurable gate array (ODRGA) to realize fast and arbitrary partial reconfiguration capabilities. This paper presents the structure of a fabricated ODRGA-VLSI chip using an optical system with vertical cavity surface emitting lasers (VCSELs) along with experimental...
The main task of the interlock system is to prevent any damage from the cost expensive components of the RF station. The implementation of the interlock should guarantee a maximum uninterrupted time of operation which implies the implementation of self diagnostic and repair strategies on module basis. Additional tasks include collection and temporary storage of status information of individual channels;...
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