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This paper describes a self-configurable middleware and a node execution platform to support autonomous sensor networks. We achieve self-configuration by scheduling and strategies similar to load balancing (mapping) that is integrated in our proposed middleware. On the node execution platform we decide on the fly between microprocessor and FPGA realization of hybrid tasks. We propose a combination...
Handheld devices are expected to start using fine-grained ASIC accelerators to meet energy-efficiency requirements of increasingly complex applications, e.g., video decoding and reconfigurable radio. To avoid overhead, static multiprocessor schedules are preferable for orchestrating fine-grained accelerators. However, as modern applications use accelerators in irregular patterns, static scheduling...
Reconfigurable computing systems allow executing tasks in a true multitasking manner. Such systems share the reconfigurable device and processing unit as computing resources which leads to highly dynamic allocation situations. To manage such systems at runtime, a reconfigurable operating system is needed. The main part of this operating system is resource management unit which performs HW/SW partitioning,...
The possibility of using Evolvable Hardware (EHW) for scheduling real-time traffic in Asynchronous Transfer Mode (ATM) networks have studied in this paper. EHW is hardware built on programmable logic devices and whose architecture can be reconfigured by using genetic learning to adapt to new environments. A novel design is the function-level EHW based on Field programmable Gate Array (FPGA) chips...
Mobile video processing as defined in standards like MPEG-4 and H.263 contains a number of timeconsuming computations that cannot be efficiently executed on current hardware architectures. The authors recently introduced a reconfigurable SoC platform that permits a low-power, high-throughput and flexible implementation of the motion estimation and DCT algorithms. The computations are done using domainspecific...
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