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The basic theory of Digital Down Converter (DDC) in digital receiver was discussed in this paper. Xilinx ISE 13.3 software was chosen to design each module of DDC. Then use the Modelsim 6.5 function simulation to verify the functionality correctness of the design. The output signal was simulated in Matlab to analyse the results.
To enable 40Gb/s data transmission over optical fibres using QPSK modulation, the first step of the receiver signal-processing pipeline is a 128-tap FIR filter that compensates the chromatic dispersion due to the medium. We present an implementation of this FIR filter in the largest Stratix-IV GX device that is able to process 20 giga-samples per second, where each sample is a complex number with...
Digital Signal Processing is a curriculum closely integrated by theory, implementation and application. With the development of microelectronics technology in recent years, the emergence of variety of chips makes digital signal processing widely used in various fields. Therefore, almost all of the electronic and computer engineering departments are now offering the digital signal processing courses...
Finite impulse response(FIR) Band-pass filter is widely used in many digital signal processing. Its advantage is good linear phase character for designing any amplitude frequency characteristic, which is very critical to real-time digital signal processing. In this paper, we analyzed the filter's structure and traditional algorithms, and pointed out the weakness, and then proposed an optimal distributed...
At first, this paper analyzes the basic structure and hardware characteristics of the FIR digital filter, and then a design method of the FIR filter is discussed on the basis of the FIR filter structure. It is a method that is based on FPGA, draws the coefficient by Matlab and adopts the pipeline to implete the FIR digital filter. The article focuses on the introduction of the overall framework of...
This paper describes a synthesis design from the MATLAB model into VHDL of a digital interpolation filter algorithm, used in a ΔΣ digital-to-analog converter (DAC), intended for Professional digital audio system. The whole filter system simulation, VHDL implementation and field programmable gate array (FPGA) verification are processing. The register transfer level (RTL) simulation result show an achieving...
This paper presents a new filter design method for protective relaying system for power line carrier according to the characteristic of noise. Making advantages of FPGA (field programmable gate array), Matlab and DSP tools, this paper designs a good performance IIR filter which is implemented in FPGA. The results of simulation show that the method is effective.
A multi-stage digital decimator for sigma-delta analog-to-digital converter with an oversampling ratio of 64 is described. To optimize the architecture of the digital filters and the circuit implementation, multi-rate multi-stage decimation, half-band filter and multiplier sharing are used. The filter is designed and simulated using SIMULINK and MATLAB while the hardware realization is obtained using...
In this paper, we deal with the design and practical implementation of a decimation filter used for high performance audio applications. We implemented the decimation filter using the canonic signed digit (CSD) representation. The decimation filter was simulated using Matlab, and its complete architecture was realized using DSP Blockset and Simulink. The filter was implemented using Mentor Graphic...
This paper describes the design of Transposed Form FIR filter implemented in the Spartan-II and Virtex-E family of FPGAs. The design is an 8-tap filter based on 16-bit input samples and 14-bit signed coefficients. The basic building blocks of the filter are KCMs, Adders, Registers, and a delay-locked loop. All the 14-bit coefficient factors are stored with an 18-bit word size in the ROM. The program...
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