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The objective of the paper is to present a work concerning an adaptive digital controller for satellite medium power DC/DC converters that is done in Space Research Centre. The presented adaptive techniques and methods allow the controller that was implemented in VHDL, to modify its properties according to detected changing conditions like inductor entering from discontinuous to continuous current...
A regulated linear dual-tuning differential ring oscillator has been designed and fabricated in UMC 0.13 µm CMOS process for ultra wide band (UWB) applications. The integrated voltage regulator has a robust performance with high power supply rejection ratio to improve phase noise performance at the presence of power supply ripple. The proposed dual-tuning technique enables a wide tuning range covering...
A three stage ultra low power, low voltage ring oscillator is presented in this paper. The bulk of the PMOS transistor is used as the control voltage, the substrate of the NMOS transistor is also forward biased to reduce the threshold of the NMOS transistor for low voltage operation. The proposed VCO is designed and simulated in 0.18 ??m RF CMOS process. Simulation results show that the proposed VCO...
This document presents a compilation of results from tests performed by iRoC Technologies on SER induced by alpha particles on SRAM memories for technology nodes from 180 nm to 65 nm. The aim of this study is to establish the variation of sensitivity with technology node for SEU and MCU, and to analyze the possible influence of different designs and technological parameters at a given technology node.
The implementation of complex functionality in low-power nano-CMOS technologies leads to enhance susceptibility to parametric disturbances (environmental, and operation-dependent). The purpose of this paper is to present recent improvements on a methodology to exploit power-supply voltage and temperature variations in order to produce fault-tolerant structural solutions. First, the proposed methodology...
Polymorphic gates can be considered as a new reconfigurable technology capable of integrating logic functions with sensing in a single compact structure. Polymorphic gates whose logic function can be controlled by the level of the power supply voltage (Vdd) represent a special class of polymorphic gates. A new polymorphic NAND/NOR gate controlled by Vdd is presented. This gate was fabricated and utilized...
Class D amplifiers are becoming the most feasible solution for embedded audio application. However, distortions due to the non-linear nature of switching stage are the main drawback for this amplifier topology. This paper discusses the design and implementation of high fidelity audio class D using sliding mode control scheme. This design method proves to be a cost effective solution for industrial...
A high bandwidth critical path monitor (1 sample/ cycle at 4-5 GHz) capable of providing real-time timing margin information to a variable voltage/frequency scaling control loop is described. The critical path monitor tracks the critical path delay to within 1 FO2 inverter delay with a standard deviation less than 3 FO2 delays over process, voltage, temperature, and workload. The CPM is sensitive...
A circuit for on-chip measurement of long-term jitter, period jitter, and clock skew, is demonstrated. The circuit uses a single latch and a voltage-controlled delay element, and is evaluated in a stand-alone pad frame. Excellent reproduction of jitter measured by oscilloscope is shown. Measured jitter resolution is 1 ps or better. The circuit is also incorporated into a 2 GHz clock distribution network...
We propose a dynamic voltage boosting (DVB) method for improving performance by slightly boosting voltage within a withstand voltage. We measured an improvement of 44%voltage drop with about 10 % area overhead in a 65 nm CMOS. This DVB method combined with a series power gating can be used to achieve high performance for low-cost low-power SoCs in advanced process technology.
The device design, fabrication and characterisation of NMOS and PMOS transistors of a 0.25 μm CMOS technology will be discussed. The devices were optimized for a reduced power supply voltage of 2.5 V. High quality devices with good control of short channel effects were obtained. Hot carrier degradation experiments showed that NMOS devices could operate at 2.5 V supply voltage. The delay per stage...
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