The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
In this paper, the characteristics of on-chip rectangular coaxial line (RCL) are analyzed and a single-pole single-throw (SPST) switch is demonstrated utilizing the RCL in a standard 0.13-μm CMOS technology. The characteristic impedance of the RCL is promoted to 20-54Ω range, which makes it convenient to design a 90° hybrid coupler. A SPST switch at W-band is designed utilizing the coupler and the...
This paper proposes a transformer-based class-E CMOS power amplifier (PA) with shunt LC network. The conventional class-E PA circuits contains a series inductor and capacitor in the load network; the proposed class-E PA was realized only with a pair of inductor and capacitor connected in shunt at the output load network. The shunt network exhibits a higher quality factor Q with a finite value of shunt...
Leakage currents are one of the major design concerns in Deep sub-micron (DSM) technology due to rapid integration of semiconductor industries by reducing the transistor size. Many parameter has been reduces with technology scaling such as Threshold voltage, oxide thickness, channel length and supply voltage (Vdd) has been reduced to keep power consumption under control. As a consequence, the transistor...
The market demand and efficient portable electronic equipment have pushed the industry to produce circuit designs operating at low voltage (LV) for low power (LP) consumption. Reducing the supply voltage reduces the dynamic power quadratic ally and leakage power linearly to the first order. Hence, supply voltage scaling has remained the major focus of the low power design. This has resulted in circuits...
This work describes the design and implementation of an inductorless, low power, high conversion gain fully differential subharmonic down-conversion mixer for 2.4 GHz application. A complementary current-reuse technique is adapted between the transconductance stage and LO switching stage to boost the conversion gain without additional power consumption by reusing the DC current of the LO switching...
A high-speed folded-cascode OP Amp with a dynamic switching bias circuit, which enables low power consumption, high gain stably, and a relatively wide dynamic range in low power supply voltages, is proposed. Through simulations, it was shown that the OP Amp is able to operate at a 10 MHz dynamic switching rate and a dissipated power of 71 % of that observed in continuous operation. It also showed...
A 6-bit low power current steering data to analog converter (DAC) which sampling frequency up to 8GHz is presented. The converter consists of 4MSBs and 2LSBs, trading off between the precision and complexity of circuit. The 8-GSample/s conversion rate has been obtained by fully custom designed thermometer decoder and synchronization circuit. The spurious free dynamic rang (SFDR) more than 34.2 dB...
CMOS logic is extensively used in VLSI circuits but due to scaling of technology, the threshold voltage of the transistors used in CMOS circuits decrease which cause an increase in leakage power. Dynamic power consumption, which is proportional to square of supply voltage VDD further adds to the overall power dissipation. This results in low battery life of mobile devices. In this brief, a novel method...
A low-cost silicon-based high efficiency CMOS-LDMOS switch-mode power amplifier (SMPA) line-up operating for sub-1GHz application is presented. The switch-mode operated LDMOS device is driven by high-speed, high voltage driver, implemented in a standard 0.14µm CMOS process technology. The CMOS driver uses high voltage extended-drain devices and delivers a 5.0VPP output voltage swing up to 1GHz. The...
This paper presents an X/Ku-band bi-directional true time delay T/R chipset in 0.13 µm CMOS technology for wideband phased array antenna. The T/R chipset comprises of wideband bi-directional distributed gain amplifiers (BDGA), a 7-bit true time delay (TTD) circuit, and a 6-bit digital step attenuator. The tuning bits are included in TTD (2-bit) and DSA (2-bit) for the amplitude and group delay error...
A new load-insensitive class-E power amplifier mode is presented that that enables frequency reconfigurability by statically changing the switch duty-cycle without compromising its tuned efficiency performance. The technique is tested on a prototype CMOS-GaN class-E Chireix power amplifier designed for 1.8–2.2 GHz. The drain efficiency is more than 55% at 8dB back-off and more than 60% at 6dB back-off...
A track-and-hold amplifier using 65 nm CMOS process is presented in this paper. The cascode topology with inductive peaking technique is employed to enhance voltage headroom and bandwidth. The input parasitic capacitance of the output buffer is designed as the hold-mode element to further reduce chip size. The dc supply voltage is 1.8 V with a total power consumption of 197 mW. When the input frequency...
Modern communication and signal processing is dependent on the high speed and low power consumption of the Analog-to-Digital converters (ADC) to a very large extent. Comparator is the basic building block of the ADCs which compares the two set of variables and change the input analog signal in digital. In this paper a new design of double tail comparator is proposed for high frequency of data conversion...
Millimeter-wave switching power amplifiers are developed both in V-band and in W-band targeting successful line-up implementations in low-power transmitter applications using 45nm SOI CMOS process. The single power-stage V-band power amplifier is designed using mixed switching mode class-ElF topology and achieves 10dBm Psat, 20% peak PAE and >45% drain efficiency at 52GHz from 1.0V supply. This...
A low power CMOS voltage reference using body effect and switched-capacitor technique is presented in this paper. The output voltage is produced by the gate-source voltage. The MOSFETs are working on subthreshold region thus the power consumption is greatly reduced. By utilizing the switched-capacitor technique, only one transistor is required to generate the reference voltage, so that the threshold...
Mixer is one of the main modules of a transmitter system, and its performance will heavily impact the functionality of the entire transmitter. Gilbert cell structure can achieve high degree of RF (Radio Frequency) and LO (Local Oscillator) isolation, thus loosening filtering output requirements. This paper presents a up-conversion mixer, designed in a standard TSMC0.13 μm CMOS technology, for 1.8–2...
This paper presents a high-speed CMOS OP Amp with a dynamic switching bias circuit capable of processing video signals of over 2 MHz with slight nonlinearity and low dissipated power. The OP Amp, capable of operating at 10 MHz dynamic switching rate, was designed and showed through simulations a dissipated power of 60 % of that in conventional continuous operation. A switched capacitor (SC) non-inverting...
With the advent of battery operated devices and scaling trends in deep submicron (DSM) regime, leakage power is becoming large component of total power dissipation. In this paper leakage reduction techniques viz. Stack forcing and Multi-Threshold CMOS (MTCMOS) have been implemented on CMOS, Complementary Pass Transistor Logic (CPL), and Transmission Gate (TG) logic style based digital circuits. The...
The exploitation of multiple-input multiple-output (MIMO) benefits in the radio frequency (RF) domain adds special restrictions to the mixer design. This paper proposes a passive mixer core, which can be employed for both conversion directions in wireless local area network (WLAN) transceiver integrated circuits (ICs). Because in highly integrated direct conversion receivers an unknown level of self-mixing...
A low-power switchable quad-band CMOS LNA for PCS(1.8 GHz), WCDMA(2.1 GHz), WiBro(2.3 GHz), and LTE(2.6 GHz) applications is presented. The proposed LNA has an advantage of occupying less chip area compared to other concurrent topology which uses more inductors by adopting LC tank resonators. Also, it consumes less current compared to other topology which adopts a switched parallel transistor technique...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.