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This paper investigates the thermal cross-talk between the powered microbumps under one chip and the un-powered microbumps under the neighboring chip. Both chips were on a Si interposer for 2.5D IC. The Joule heating from the powered chip was found to be transferred laterally along the interposer to the unpowered chip and produced a temperature gradient in the microbumps in the unpowered chip. Void...
Ultrathin film electroless deposition of Cu and Ni is shown for IC and TSV barrier layer / interconnect applications as an alternative to vacuum based deposition techniques. Cu films of approximately 20 nm were achieved while coherent electroless Ni can be deposited to single digit nm levels. The use of self-assembled monolayers facilitates electroless deposition in high aspect ratio structures. This...
In this paper we deal with cooperative fuzzy games with communication networks. We introduce the concept of fuzzy core for network-restricted fuzzy games and present a sufficient and necessary condition for the inheritance of existence of the fuzzy cores. We also study the effect of communication networks on the properties of superadditivitiy, monotonicity, and convexity.
Atomic-scale computational materials engineering offers an exciting complement to experimental observations, revealing critical materials property data, and providing understanding which can form the basis for innovation. This contribution reviews the current state of atomic-scale simulations and their capabilities to predict mechanical, thermal, and electric properties of microelectronics materials...
Graphene has been shown to have an extraordinary set of electronic properties and its chemical affinity is readily tuned by functionalization with a broad range of molecules. It is known that field effect transistors based on single-layer graphene demonstrate extremely high sensitivity for chemical sensing. It is thus very important to achieve fabrication of integrated circuits on large-area graphene...
Software-based self-test (SBST) is increasingly used for testing processor cores embedded in SoCs, mainly because it allows at-speed, low-cost testing, while requiring limited (if any) hardware modifications to the original design. However, the method requires effective techniques for generating suitable test programs and for monitoring the results. In the case of processor core testing, a particularly...
This paper presents an innovative structure based on 3 dimensional integration technology, where ultra thin inter layer dielectric enables a dynamic threshold voltage (VTH) control. A sequential process flow is proposed to fabricate 3D devices with dynamically tunable VTH. This ability can be exploited to design SRAMs cells with increased stability and surface density compared to planar technology...
Graphene is a possible candidate for advanced channel materials in future field effect transistors. This presentation gives a brief overview about recent experimental results in the field of graphene transistors for future electronic applications.
Bulk nanostructured (Bi,Sb)2Te3 compounds and GeTe based amorphous/nanocrystal composites have been successfully fabricated by the combined hydrothermal/hot-pressing and quenching/annealing methods, respectively. The (Bi,Sb)2Te3 nanopowders synthesized by hydrothermal method exhibit a hollow-like structure. After hot-pressing, the nanoscale grains varying from tens to hundreds of nanometers were found...
Nanostructuring is one of the effective approaches to lower the thermal conductivity of materials. Nanostructured skutterudite-related compounds CoSb3, Fe0.5Ni0.5Sb3, Fe0.25Ni0.25Co0.5Sb3 and Te-doped CoSb3 were synthesized by a solvothermal route. The bulk materials were prepared by hot pressing or spark plasma sintering from the solvothermally synthesized nanopowders. The thermal conductivity values...
This paper presents a new algorithm for channel routing of multiterminal nets. We first transform any multiterminal problem of density d to a socalled extended simple channel routing problem (ESCRP ) of density 3d/2+O(√dlog d), which will then be solved with channel width w ≤3d/2+O(√dlog d) in the knock-knee model. The same strategy can be used for routing in the other two models: The channel width...
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