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Integration of analog and digital circuits is a vital design issue in mixed signal circuits. Switching activity at the digital end widely affects the analog circuitry. This paper presents the generation and variation of substrate current due to the switching activity in a digital circuit and also how the substrate current varies with the switching frequency. The circuit under test is a CMOS inverter...
This paper presents ultra low-power adiabatic flip-flops that operate on near-threshold region. The near-threshold flip-flops are realized by PAL-2N (pass-transistor adiabatic logic with NMOS pull-down configuration) circuits. A near-threshold mode-10 counter is verified. All circuits are simulated using NCSU PDK 45 nm technology by varying supply voltage from 0.2 V to 0.9 V with 0.1 V steps. Based...
The paper presents a test calculation principle which serves for producing tests of switch-level logic faults in CMOS digital circuits. The considered fault model includes stuck-at-0/1 logic faults on the connecting control lines, as well as switch faults in the transistors. Both single and multiple faults are included. The transistor faults manifest themselves in stuck open (open circuit) and stuck...
With technology scaling, vulnerability to soft errors in random logic is increasing. There is a need for on-line error detection and protection for logic gates even at sea level. The error checker is the key element for an on-line detection mechanism. We compare three different checkers for error detection from the point of view of area, power and false error detection rates. We find that the double...
An on-chip buck converter with 3D chip stacking is proposed and the operation is experimentally verified. The manufactured converter achieves a maximum power efficiency of 62% for an output current of 70mA with a switching frequency of 200MHz and a 2x2mm on-chip LC output filter in 0.35mum CMOS. The use of glass epoxy interposer to increase the maximum power efficiency up to 71.3%, and the power efficiency...
This paper introduces a novel current sense amplifier (CSA) in sub-32nm fully depleted (FD) double-gate (DG) silicon-on-insulator (SOI) technology with planar independent self-aligned gates. A new architecture is proposed which takes advantage of the back gate in order to improve circuit properties. Compared to the reference circuit, the new architecture proves to be faster (21% sensing delay decrease),...
In deep submicron era, to prevent larger amount of SRAM from more frequently encountered overheating problems and react accordingly for each possible hotspots, multiple ideal run-time temperature sensors must be closely located and response rapidly to secure system reliability while maintaining core frequency. This paper presented a method to extract run-time temperature information from multiple...
We present a new logic family, Differential Current Switch Logic (DCSL) for implementing clocked CMOS circuits. The circuit is in principle a differential cascode voltage switch logic circuit (DCVS). In comparison to other forms of clocked DCVS, DCSL achieves better performance both in terms of power and speed by restricting internal voltage swings in the N tree. Automatic lock-out of inputs on completion...
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