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This paper proposed a novel layout for cross-coupled pair to reduce its extrinsic resistive and capacitive parasitic parameters and another layout for differential pair to decrease the influence of Miller effect and some other parasitic effects. The equivalent circuits of the extrinsic parasitic network of these two structures are first derived and validated using EM simulation. The extraction equations...
The consequences of the current electronic equipment market demands is causing designers to develop ever faster circuits in ever smaller devices. The miniaturization of circuits together with increased operating speeds shows several functional difficulties, which require skills and knowledge of the designer so that the final product fits into operation standards and can be produced. The objectives...
The inductance of a helical inductor is related to the self inductance of each line segment and mutual inductance between line segments. As mutual inductance is dependent on the distance between coupled metal lines within helical inductors, mutual inductance in traditional straight line helical inductors is susceptible to layer-to-layer misalignment during fabrication if two coupled lines are located...
We present the design and measurements of a Heterostructure Barrier Varactor based frequency tripler for 280 GHz. The tripler is fabricated as a monolithic circuit on an InP substrate, including the input and output waveguide probes. Several circuit versions for input power levels between 100 mW and 1W have been designed.
Aggressively applied function and geometry oriented partitioning is proposed for design and analysis of RF harmonic filters. The efficiency of the proposed methodology is demonstrated by application to the RF portion of an NXP semiconductor transceiver design. Simulation is compared to measurement at both component and function-block levels. Limits of partitioning assumptions in comparison with full-electromagnetic...
A design environment for stripe-shaped PMELA TFTs on glass has been developed and successfully tested. Cell library including standard cells, logic synthesis database, place and route rule, layout parasitic extraction rule and transistor models are developed. Measurement results show that the digital circuits designed in this environment work correctly. They also show that the simulation environment...
Through this work we highlighted and demonstrated the significance of an algorithmic way of design and development of CMOS LNAs at 5 GHz. The systematic design led to very good measured performances of 14 dB gain, 1.78 dB noise figure, 10 dB return loss both at the input and output and a high linearity of-3 dBm of IP3 under 5.4 mW power consumption. These results compare the best performances reported...
While the CMOS analog circuits can be designed with the minimum-gate-length of the fabrication process in the alpha-power law MOSFET model, the length of a MOSFET gate has been chosen to be a larger scale than the minimum-gate-length in the conventional Shockleypsilas square model. In this paper, we describe a 6-b 100 MSPS CMOS current steering digital-to-analog converter (DAC) with the alpha-power...
In this paper the possibility of using a low cost SiGe:C BiCMOS technology dedicated to few GHz applications up to 30 GHz is discussed. Spiral inductors with SRF higher than 30 GHz, are not available at the foundry library. Accordingly, inductors with a SRF higher than 45 GHz were obtained, however their Q is only 5 at 30 GHz. The test and modeling technique is presented. The design, implementation...
This paper provides a short review of radio frequency/microwave power amplifiers (PAs) and their critical role in a modern satellite communication system. Authorspsila original design contributions are also highlighted.
In this paper, the design of a compact planar bandpass filter above a defected ground plane is presented. The filter is designed as a combination of microstrip resonators and exploits the properties of a planar electromagnetic bandgap (EBG) structure patterned unto the ground plane of the printed circuit board material to provide a very wide stopband of up to 5 times the fundamental frequency. The...
A high intercept points, cost-effective, and power-efficient switching FET double balanced mixer (DBM) is reported. The Switching FET DBM demonstrated in this work offers input intercept points (IIP3) and conversion loss typically 44 dBm and 8.5 dB respectively with 15 dBm LO power for the frequency band (RF: 900-2150 MHz, LO: 850-1950 MHz, IF: 50-200 MHz). The measured interport isolation is typically...
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