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We present an energy efficient QRS detector for real-time ECG signal processing implemented in ASIC. An adaptive thresholding scheme based on forward search interval (FSI) algorithm together with simple preprocessing is proposed to accurately detect QRS peaks. The Verilog HDL codes with improved hardware utilization efficiency are validated using FPGA, achieving 99.59% sensitivity (Se) and 99.63%...
Application specific integrated circuits (ASICs) are commonly used to implement high-performance signal-processing systems for high-volume applications, but their high development costs and inflexible nature make ASICs inappropriate for algorithm development and low-volume DoD applications. In addition, the intellectual property (IP) embedded in the ASIC is at risk when fabricated in an untrusted...
Multipartite table methods offer a high speed, low area implementation of commonly used functions for up to 24 bits of accuracy. Currently the parameters which dictate the configuration of these tables are chosen using a worst-case rounding approximation scheme which often generates sub-optimal results. This paper will show that it is possible to perform a full exhaustive search to find the minimum...
The top level systems engineering of a digitally beam formed phased array for high throughput satellites is described. The focus of this work is on demonstrating that a viable concept exists by partitioning the system and showing a technology path for the subsystems. The system design is supported by trade studies which justify technology choices. Also, applicable industry standards for digital interfaces...
A high performance implementation of an algorithm based on the learning process of the human vision as an edge-enhancing filter for medical images is proposed. It is based on a cognitive image processing algorithm that emulates the contour identification process that is believed to be used by the human brain. The algorithm is implemented on an innovative and high performance embedded system for real-time...
Novel methods for unauthorized access are always made. For cyber security measures in mobile devices, low-power and high-speed processing is very important. Despite these situations, a CPU for mobile devices is a very low processing capacity in order to focus on low-power operations and does not have sufficient performance for processing detection processing for unauthorized access. In contrast, a...
Taking advantage of synchronous and asynchronous paradigms, a new style of design, called Globally Synchronous Locally Asynchronous (GSLA), has achieved very interesting results. In this paper, we propose a synchronous wrapper that allows the communication of “synchronous to asynchronous to synchronous” modules. Internally, the proposed interface comprises an asynchronous module. The GSLA design style...
Los Alamos National Laboratory has designed and manufactured a single-board computer (SBC) for deployment in space-flight applications. The SBC is designed to meet the command- and data-handling requirements for missions requiring true space-grade radiation hardness and fault tolerance, exceeding those that are typical in CubeSat and SmallSat applications but at a substantially lower cost, lower power,...
An area efficient and high speed architecture design of hard decision Viterbi decoder with encoding rate of 1/2 and constraint length of k = 3 is presented in this paper for the application in satellite communication. The proposed Viterbi decoder is implemented in field programmable gate array (FPGA) and also in application specific integrated circuit (ASIC) using UMC 0.18 µm technology where the...
This paper describes the technology-independent approach for FPGA (Field-programmable gate array) and ASIC (Application Specific Integrated Circuit) implementations. This approach is based on the reuse of portable building blocks described at RTL level, thus the design can be mapped to an ASIC or an FPGA devices with few RTL code changes when migrating between FPGA and ASIC. As case study, an OpenRISC...
Many applications use encryption to protect data confidentiality, which require decryption before any data processing. Integrating ASIC design of encryption engines and general-purpose processor can yield the best overall performance in program execution as it benefits from low latency hardware engine and high processor memory bandwidth. However, ASIC design is fixed once manufactured, which cannot...
“Digital at every element” (elemental digital) arrays have many compelling advantages, at least in theory. A persistent drawback of elemental digital arrays has been their perceived high costs and the challenges of placing high performance data converters at each element. New device technologies and fabrication lines are beginning to break down the cost challenge, making elemental digital arrays of...
Reconfigurable embedded devices built on SRAM-based Field Programmable Gate Arrays (FPGA) are being increasingly used in critical embedded applications. However, the susceptibility of such memory cells to Single Event Upsets (SEU) requires the use of fault tolerant designs, for which fault injection is still the most accepted verification technique. This paper describes FIRED, a fault injector targeted...
This paper presents design and preliminary performance of a mixed-signal front-end electronics dedicated to CZT detectors. It is implemented by a full-customized readout application-specific integrated circuit (ASIC) with a post digital pulse shaping algorithm in FPGA. In this scheme, the analog front-end consists of a preamplifier using split-let topology followed by a variable gain amplifier. A...
We present an ASIC architecture with coarse-grain reconfigurability that uses accelerators to improve performance over fine-grain reconfigurable architectures. A reconfigurable FFT ASIC was built as a proof of concept, and it successfully demonstrated valid switch operation for reconfiguration.
Hardware implementations of statistical tests are needed to detect failures and statistical weaknesses of entropy sources in True Random Number Generators on the fly. Current implementations of these tests work under the assumption that the entropy source produces independent, identically distributed (IID) numbers. However, some entropy sources produce non-IID data and rely on compression to provide...
In this paper, we propose RadixBoost, a hardware acceleration structure for scalable 32-bit integer radix sort on GPU. The whole structure is integrated into a GPU microarchitecture as a special functional unit and can be started by new instructions. Our design enables a significantly faster sorting procedure for general purpose GPU computing. The RadixBoost architecture was validated by an FPGA prototype...
This paper investigates the possibility of creating an energy profile of a RISC processor instruction set in the prototyping phase, using FPGA implementation and physical measurements. In order to determine the power consumption at instruction-level, several programs have been developed and run on the processor implementation on FPGA. The experiments have focused at the following groups of instructions:...
The Aim is to HDL Design & Implementation for 20 Tbps Multichannel 64:1 LVDS Data Serializer & De-Serializer ASIC Array Card for Ultra High Speed Wireless Communication Products like Network On Chip Routers, Data Bus Communication Interface Applications, Cloud Computing Networks, Terabit Ethernet at 20 Tbps Rate Of Data Transfer Speed. Basically This Serializer Array Converts 64 bit...
This paper considers the system architecture and design issues for implementation of on-line Model Predictive Control (MPC) in Field Programmable Gate Arrays (FPGAs) and Application Specific Integrated Circuits (ASICs). In particular, the computationally itensive tasks of fast matrix QR factorisation, and subsequent sequential quadratic programming, are addressed for control law computation. An important...
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