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As the scaling of conventional MOSFETs approaches its technological limit, the double-gate (DG) MOSFETs have emerged as an important candidate for the next generation device. As a novel device with an additional fourth terminal, the DG devices have a potential to evolve not only in the More-Moore way, i.e. short channel effects and variation prevention, but also in the More-than-Moore direction, i...
The unstable/unpredictable LSI operation caused by the PVT (Process Voltage Parameter) variations, along with the aging effect such as NBTI/PBTI, is one of the serious issues in current and future scaled LSIs. In these situations, where operation environments in the field are hard to predict at the stages of circuit design and test, the conventional approach of the margin-based design and test in...
With the increasing NRE cost of advanced process technologies, reconfigurable devices receive great attention in small and medium volume IC designs. However, lower logic utilization and slower timing performance limit the efficacy of FPGA and CPLD. In this paper, we propose an efficient hybrid LUT/SOP reconfigurable design style to exploit both the advantages of LUT-cell and SOP-cell for circuit design...
The following topics are dealt with: analog circuits; signal and data processing; mixed-signal circuit techniques; CAD tools for advanced SOCs; field programmable gate arrays; CAD for VLSI; circuit design and; nanoelectronics.
Programmability and flexibility are the trend of current electronic system. The Nios, a soft-core processor integrated in a FPGA chip, is characterized by its flexibility and programmability. Since its introduction in June 2000, Altera's Nios soft-core processor has rapidly been integrated in a wide range of applications. In this paper, design and realization of the hardware platform based on the...
The majority of configuration bits affecting a design are devoted to FPGA routing configuration. We present a SEU-aware routing algorithm that provides significant reduction in bridging faults caused by SEUs. Depending on the routing architecture switches, for MCNC benchmarks, the number of care bits can be reduced between 13% and 19% on average with comparable delay, hi addition, in asymmetric SRAM...
In this paper, circuit design of an arithmetic module applied to cryptography - modulo multiplicative inverse is presented and implemented using FPGA hardware technology. This modular arithmetic function contains iterative computations of division, multiplication and accumulation with variable loop times. Besides standard HDL programming and schematic input, Simulink-to-FPGA has been tried as a different...
The implementation of inverse kinematics and servo controller for robot manipulator using FPGA (field programmer gate array) is investigated in this paper. Firstly, the mathematical model and the servo controller of robot manipulator are described. Secondly, the inverse kinematics is formulated. Thirdly, the circuit design to implement the function of inverse kinematics and servo controller based...
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