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As a important step in SoC design, good architecture design is the foundation to ensure the final structure to meet the design specifications. In paper, the minimal SoC system used for performance compare between basic architectures is defined, which is consisted of embedded processor, on chip bus, on chip memory and IP (GPIO). Then six SoC architecture based on 32 bit embedded RISC processor is studied,...
A System-on-Chip (SoC) offers an optimal implementation of electronics for portable medical systems and in particular for Body Area Network (BAN) applications. It integrates as much functionality as possible into a single chip thereby allowing miniaturization of the system, while optimizing performance and power consumption. Using today's mature and cost effective semiconductor process CMOS technology...
In this paper, we present the design of a baseband System-On-Chip for tracking applications in the medical environment based on the IEEE 802.15.4 standard which can be used to track patient location in hospitals. It utilizes an ARM Cortex-M1 soft-core, 16 kb of SRAM and a bus architecture based on the AHB-Lite specification. The IEEE 802.15.4 MAC primitives are implemented in a Flash-ROM of 32 kb...
To meet the growing needs of computing power, communication speed and performance requirements demanded by today's applications, processor clock speed has to be increased. However, increasing clock speed is not viable due to heat dissipation and power consumption constraints. Hence Instead of trying to increase the clock speed, multi-core processor architectures with the lower frequency can be used...
Power profiling methods are indispensible in the power-aware design of HW/SW systems. By extending functional emulators with power estimation hardware, high-level power information can be derived during run-time, yielding a considerable speed-up as compared to simulation based approaches. A key enabler for the widespread use of the power emulation methodology is the automation of both power model...
Starting from sequential programs, we present an approach combining data reuse, multi-level MapReduce, and pipelining to automatically find the most power-efficient designs that meet speed and area constraints in the design space on Field-Programmable Gate Arrays (FPGAs). This combined approach enables trade-offs in power, speed and area: we show 63% reduction in power can be achieved with 27% increase...
To cope with increasing in-field failure rates for cost-sensitive electronic products, a low-overhead online checking methodology - Time-Multiplexed Online Checking (TMOC) - was proposed and demonstrated (see IEEE Asian Test Symposium, p.371-6, 2008). In this paper, we study the area overhead required for employing TMOC in an embedded field programmable gate array (eFPGA) core. The overheads caused...
The increasing processing capability of Multi-Processor Systems-on-Chips (MPSoCs) is leading to an increase in chip power dissipation, which in turn leads to significant increase in chip temperature. An important challenge facing the MPSoC designers is to achieve the highest performance system operation that satisfies the temperature and power consumption constraints. The frequency of operation of...
In deep submicron era, to prevent larger amount of SRAM from more frequently encountered overheating problems and react accordingly for each possible hotspots, multiple ideal run-time temperature sensors must be closely located and response rapidly to secure system reliability while maintaining core frequency. This paper presented a method to extract run-time temperature information from multiple...
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