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Content addressable memory (CAM) performs parallel data search at the cost of high area and power penalty. We propose a high-speed 6T-ReCSAM (Reconfigurable CAM/SRAM) with new energy efficient sensing technique. Proposed implementation is compatible with compact 6T-SRAM foundry bitcells. Test-macro of 8Kb is implemented in 28nm FDSOI CMOS and reaches up to 1.56GHz at 0.9V with 0.13fJ/bit energy consumption...
Platforms with different computation resource, e.g. CPUs and FPGAs, become one of the first choices to deploy performance-requiring embedded applications. On this technology, functionalities can be implemented either as hardware (HW) or software (SW) components. Here, we extend the MultiPar methodology to support the selection of optimal partitioning solutions with respect to system properties. We...
We present our initial design implementation of a controlling and processing core circuit that is part of our RF implantable system for monitoring physiological parameters of small laboratory animals. The circuit is prototyped and experimentally verified using an FPGA development platform, then synthesized and simulated in 130nm CMOS IC technology using standard digital cells. Thus, the overall core...
Power-constrained computing is now becoming essential paradigm in both high performance computing and embedded systems. Power budget is dynamically assigned to each computing resource for improving energy efficiency and system throughput. Modern computer systems have accelerator devices, such as GPUs and FPGAs, for higher energy efficiency and performance. Therefore, power management mechanisms of...
We propose three methods for reducing power consumption in high-performance FPGAs (field programmable gate arrays). We show that by using continuous hierarchy memory, lightweight checks, and lower chip voltage for near-threshold voltage computation, we can both reduce power consumption and increase reliability without a decrease in throughput. We have implemented these techniques in two different,...
This paper contains designing of energy efficient memory circuit using two different IO standard i.e. LVTTL and Mobile-DDR on 28nm (Artix-7) Field Programmable Gate Array. We are using Xilinx ISE simulator version 14.2, Verilog hardware description language and Artix-7 FPGA. The design has been tested at different operating frequencies of Latest Intel processor that are at Intel I-3, Intel I-5 and...
Accurate characterization of real device samples is essential for understanding the true potential of the emerging non-volatile memories (NVMs) and identifying their optimal placement in the memory hierarchy. Even though, NVM devices are now available from different manufacturers, lack of an appropriate NVM controller and evaluation platform in the public domain is the main challenge in extracting...
Content Addressable Memories (CAMs) have been widely used to implement various high speed search functions in network devices such as routers and servers. In these devices, the role of CAM is to classify, drop or forward internet packets (i.e., packet classification). However, CAM suffers from several shortcomings such as high power consumption and low integration density. In addition, CAM is not...
The independent living of the elderly population is very much of a concern and threaten due to their high tendency in falling. As the worldwide aging population grows tremendously, there is a need of reliable fall detection solution which operates in real-time at high accuracy and supports large scale implementation. Highly promising tool like Field Programmable Gate Array (FPGA) had been commonly...
In this work, Virtex-6 is Target 40nm FPGA Device. Xilinx ISE 14.1 is an ISE Design tool. RAM is a target design. Clock Gating is a technique which decreases clock power but increases Logic Power due to added Logic in Design. Irrespective of increase in number of Signal and IO buffer due to Clock Gating, there is significant decrease in IO Power and Dynamic Power due to decrease in number of frequency...
Data acquisition (DAQ) is a crucial component in instrumentation and control. It typically involves the sampling of multiple analog signals, and converting them into digital formats so that they can be processed. DAQ systems also involve microprocessors, microcontrollers, digital signal processing, and/or storage devices. Many multi-channel DAQs, which utilize some sort of processing for simultaneous...
Both Internet and semiconductor technology have advanced dramatically over the past decade. These advancements have made great impact on the conventional Internet infrastructure where networking equipment is dedicated on a per network basis. Router virtualization allows a single hardware router to serve packets from multiple networks while ensuring the same throughput and Quality of Service (QoS)...
Network traffic keeps increasing like as the demand of video streaming. Routers and switches in wire-line networks require guaranteed line rate as high as 20Gbp/s as well as advanced quality of service (QoS). Hybrid SRAM and DRAM architecture previously presented with the benefit of high-speed and high-density requires complex memory management. As a result it, it has hardly supported large numbers...
In this paper, we present an approach that uses information about the FPGA architecture to achieve optimized allocation of embedded memory in real-time video processing system. A cost function defined in terms of required memory sizes, available block- and distributed-RAM resources is used to motivate the allocation decision. This work is a high-level exploration that generates VHDL RTL modules and...
Considering the growing power consumption problem of FPGA, which was caused by the greatly increasing of integration density and speed of FPGA. Different from traditional occupying routing resource, lookup table and flipflop, this method is taken full advantage of FPGA memory resource and employed FPGA Memory block to implement functions of Register files without occupying routing Resource. The experimental...
To meet the growing needs of computing power, communication speed and performance requirements demanded by today's applications, processor clock speed has to be increased. However, increasing clock speed is not viable due to heat dissipation and power consumption constraints. Hence Instead of trying to increase the clock speed, multi-core processor architectures with the lower frequency can be used...
Per-flow queuing is believed to be an effective approach to guarantee Quality of Service (QoS) in high performance routers. However, its brute-force implementation consumes a huge amount of memory and is not scalable as the number of flows increases. Dynamic Queue Sharing (DQS) mechanism, in which a physical queue is dynamically created on-demand when a new flow comes and released when the flow temporarily...
Starting from sequential programs, we present an approach combining data reuse, multi-level MapReduce, and pipelining to automatically find the most power-efficient designs that meet speed and area constraints in the design space on Field-Programmable Gate Arrays (FPGAs). This combined approach enables trade-offs in power, speed and area: we show 63% reduction in power can be achieved with 27% increase...
Power consumption has become a limiting factor in next-generation routers. IP forwarding engines dominate the overall power dissipation in a router. Although SRAM-based pipeline architectures have recently been developed as a promising alternative to power-hungry TCAM-based solutions for high-throughput IP forwarding, it remains a challenge to achieve low power. This paper proposes several novel architecture-specific...
Due to their reconfigurability and their high density of resources, SRAM-based FPGAs are more and more used in embedded systems. For some applications (Pay-TV,Banking, Telecommunication ...), a high level of security is needed. FPGAs are intrinsically sensitive to ionizing effects, such as light stimulation, and attackers can try to exploit faults injected in the downloaded configuration. Previous...
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