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This paper reviews Network-on-Chip architectures with prioritization of selected data streams targeting runtime reconfigurable manycore systems. The common idea of these architectures is to minimize the latency of selected packet transmissions by either bypassing or parallelizing processing stages in routers or by using dedicated links bypassing complete routers. Potential classes of selected data...
The performance of Network-on-Chip largely depends on the underlying routing techniques, which have two constituencies: output selection and input selection. Previous research on routing techniques for Network on chip has focused on the improvement of output selection. This paper investigates the impact of input selection, and presents a novel contention-aware input selection technique for network...
In this paper, we proposed a dual flit transmission rate (DFTR) router architecture according to the property of short distance for the inter-wafer links for 3D Network on Chip (NoC). The equivalent bandwidth of the inter-wafer links can be N times wider than that of the intra-wafer links, since flit transmission rate in vertical direction can be N times fast than that in the horizon direction. Thus,...
This paper proposes a reliability-aware application mapping for mesh-based NoCs. The proposed reliable mapping, called RMAP, adds redundant communications to the application graph in order to improve the reliability of packet delivery in NoCs. The RMAP divides the application graph into two sub-graphs which have the lowest possible communication with each other. One of the sub-graphs is mapped on...
Today's Internet is facing many problems which did not take into account in its initial design, such as routing scalability, mobility and security. No matter evolutional or revolutionary solutions that are proposed in recent years, a recognized promising direction is to separate customer network from core network and separate identification from location. In this paper, we sketch out an architecture...
Networks on chip (NoC), a new packet-based design method, with a new dependable no deadlock (DND) back-tracking routing algorithm are proposed to implement artificial neural network (ANN). This system is simulated by NIRGAM NoC simulator to get system performance. Experimental results show that this proposed system has higher connection-per-second (CPS), lower communication load than the exiting other...
Reconfigurability refers to systems incorporating some form of hardware programmability, that customizes how the hardware is used using a number of physical control points. These control points can be changed periodically in order to execute different applications using the same hardware. This paper presents the design and implementation of reconfigurable switch architecture for next generation networks...
In this paper, an adaptive congestion-aware routing algorithm is proposed for mesh network-on-chip (NoC) platforms. Depending on the traffic around the routed node, the proposed routing algorithm provides not only minimum paths but also non-minimum paths for routing packets. Both minimum and non-minimum paths are based on the odd-even turn model to avoid deadlock and livelock problems. The decision...
This paper presents a new approach for solving network routing optimization problems. In particular, the goal is to optimize the traffic in the network structured event-driven systems as well as to provide means for efficient adaptation of the system to changes in the environment-i.e. when some nodes and/or links fail. Many network routing optimization problems belong to the class of NP hard problems,...
This paper presents a DC-30 GHz single-pole-four-throw (SP4T) CMOS switch using 0.13 mum CMOS process. The CMOS transistor layout is done to minimize the substrate network resistance. The on-chip matching inductors and routing are designed for a very small die area (250times180 mum2), and modeled using full-wave EM simulations. The SP4T CMOS switch result in an insertion loss of 1.8 dB and 2.7 dB...
B-ISDN is expected to support diverse applications ranging from lowest to highest bit rate communications. In this mode, information is transferred in a connection oriented fashion among communicating entities using fixed size packets know as ATM cell. The Batcher-Banyan combinational switches are one of high speed space division switches. But it finds difficulties in routing two cells with same destination...
Forwarding system is one of key components for high-performance router. In this paper, the architecture of router is described first. Then, software system of centralized router and the process of a packet are analyzed. At the end, the performance bottleneck of centralized router is pointed out. To get better performance, we propose a fast-forwarding mechanism to increase the speed of packet, which...
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