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The era of internet of things (IoT) envisions a world where electronics is integrated with our environment. This can be achieved with ubiquitous low power sensing devices. It is challenging to achieve low power computing in the IoT paradigm since most applications are data-centric. However, typical applications have low duty cycle processing where idle times can be exploited for energy savings. This...
This paper presents a power-efficient 10-bit SAR ADC. A novel comparator topology with a dynamic common-gate stage is proposed to increase the pre-amplification gain under a low power supply voltage, thereby reducing noise and offset. Statistical estimation and loading switching techniques are synergically combined to further improve the energy efficiency. Moreover, the SAR sequencer and clock generator...
In this paper, a non-overlap clock (NVC) generator for high accuracy fully differential Switched Capacitor (SC) readout circuit which is applied in Micro-Electro Mechanical System (MEMS) differential sensor is proposed. Compared with traditional generator, generating a set of non-overlap clock, this circuit generates a new set of clocks which are being nested inside the primary non-overlap clocks,...
This paper presents a clock-feedthrough compensation technique for bootstrapped switches. The proposed technique utilizes a dummy transistor to generate a reverse voltage, which compensates the input-dependent error caused by clock feedthrough effect of sampling switch. Simulation result shows the differential sampling error of bootstrapped switch reduces from 7.2mV to 1.4mV for the worst case, operating...
A novel concept instrumentation amplifier (IA) using an analog signal compression technique is suggested to achieve a large dynamic input range. A large analog input signal is segmented into a smaller analog signal to prevent saturating the analog output signal in the input stage of the IA. At the input stage, we apply a reference bias at a node between an input capacitor and an input MOS to function...
Reference drivers for charge-redistribution SAR ADCs require significant area and/or power. In this work, a low-power and area-efficient passive reference-voltage driving scheme for charge-redistribution SAR ADCs is proposed. An on-chip decoupling capacitor is pre-charged to a reference voltage during tracking phase and utilized to drive the DAC passively during conversion. The reference-voltage drops...
A compact differential voltage reference cell, which combines an original switched capacitor integrator with a digitally programmable bandgap core, is presented. The two-stage integrator maintains an always-valid output voltage while performing correlated double sampling to effectively reduce the effects of offset and flicker noise. Measurements performed on a prototype designed with the UMC 0.18...
A switched capacitor dc-dc converter with frequency-planned control is presented. By splitting the output stage switches in eight segments the output voltage can be regulated with a combination of switching frequency and switch conductance. This allows for switching at predetermined frequencies, 31.25 kHz, 250 kHz, 500 kHz, and 1 MHz, while maintaining regulation of the output voltage. The controller...
This work presents a fully-integrated sub-GHz radio System on Chip (SoC) for Low-Power Wide-Area Networks (LPWAN) and Internet of Things (IoT) applications. The receiver (RX) achieves 77dB blocker rejection and −106dBm sensitivity at 50kbps. The transmitter (TX) features a Switched-Capacitor Power Amplifier (SCPA) that delivers 13.5dBm output power. To fulfil stringent Japanese emission regulation,...
An 8b 5-GS/s Successive Approximation Register (SAR) analog-to-digital converter (ADC) is implemented in 65-nm CMOS using 16-channel time-interleaving, achieving a SNR of 43.5 dB and Figure-of-Merit (FoM) of 245 fJ/conv-step. High speed operation is achieved by optimizing the critical path in the SAR ADC loop. A sampling network with a split-array with unit bridge capacitor topology is used to reduced...
This paper presents a high-speed and power-efficient successive-approximation-register (SAR) analog-to-digital converter (ADC). A dual-DAC architecture is proposed to enhance the conversion rate by decreasing the worst-case logic delay and thus the time needed for each conversion cycle. A 1-bit redundancy is introduced to absorb the decision errors caused by the mismatch between the two DACs and to...
The requirements for data conversion in CMOS Image Sensors are increasing due to number and size of pixels and can not be met anymore by classic ramp converters. To address this issue, this paper presents a compact 14-bit two-stage Incremental-ΣΔ column-parallel ADC for use in CMOS Image Sensors. The ADC as well as a test array for a pixel matrix has been fabricated in a 110nm optical CMOS process...
An analysis of high speed sample and hold circuit in different structure is presented. Performance and area comparison between two type of sample and hold circuit in low voltage is done. These different type of circuits are simulated and layout designed in 55nm CMOS technology. Both the structures based on a bootstrap switch that can acquire analog wave forms at sampling rate of 100MHz with 10 bit...
In the past, techniques for error detection in linear digital and analog circuits using checksum codes have been developed and shown to be highly efficient. While error detection is a solved problem, error correction has proved to be difficult due to the time and area overheads involved in diagnosing failed system states and correcting them in real-time. To solve the correction problem, real-time...
In this paper, a novel 10 bit 20 MS/s, low power, pipelined ADC using both capacitor and opamp sharing techniques is proposed. In the proposed ADC, feedback capacitors in the first four stages are shared between adjacent stages in order to decrease the power dissipation of the opamps used in these stages. The opamps in the six pipeline stages are also shared between adjacent stages in pairs for further...
In this paper, a 9-bit 1.3 GS/s single channel SAR ADC is presented. In conventional SAR ADCs, the capacitive DAC size grows exponentially with respect to converter resolution. This results in both signal bandwidth and conversion speed reduction. The proposed architecture implements binary search through a redundant capacitive DAC for the 5 first MSBs and through programmable comparator thresholds...
Reversion losses are a major cause in degrading the efficiency of charge pumps (CPs) and a non-overlapping clock scheme is crucial to eliminate these losses and improve the CP's efficiency. However, employing a non-overlapping clock scheme will increase the total Silicon area and can increase the total current consumption of the CP. The increase in CP's current consumption, due to a non-overlap clock...
In this paper, a technique aiming at enhancing the conversion speed of asynchronous high resolution SAR ADCs is presented. In conventional SAR ADCs, the capacitive DAC size is growing exponentially with the converter resolution. The settling time of the MSB capacitors get thus longer, limiting the total conversion speed. This method proposes to operate a small and fast 3-bit ADC in parallel with the...
This paper describes a switched capacitor, 3rd order MASH 2-1 ΣΔ modulator, for signals with a bandwidth of 20kHz, using passive integrators implemented based on the ultra incomplete settling (UIS) concept. The UIS concept requires RC time constant values much larger than the clock period. Due to the low signal bandwidth the clock frequency is 10 MHz, which would result in large resistors and capacitors...
This paper presents a 13-bit fully-differential successive approximation register analog-to-digital converter with a hybrid DAC that is suitable for sensor applications. An innovative dithering plus averaging technique is developed around this originally-designed 10-bit ADC to make it possible to attain an effective resolution of 13 bits in a configurable fashion without calibration. The ADC has a...
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