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True Random Number Generator (TRNG) occupies a commendable position in various information security applications. Random numbers are the one which need to possess the properties of uniform distribution and statically independent. Diffused bit Generator (DBG) is a reliable entropy source and core component to produce the sequence of random bits. The bits emanating from DBG is usually further sampled...
Generic quantum-circuit simulation appears intractable for conventional computers and may be unnecessary because useful quantum circuits exhibit significant structure that can be exploited during simulation. For example, Gottesman and Knill identified an important subclass, called stabilizer circuits, which can be simulated efficiently using group-theory techniques and insights from quantum physics...
Automatic test pattern generation for non-scan sequential circuits is an extremely challenging task. If successful, it can offer many benefits to the EDA community, ranging from manufacturing and functional test to post-silicon validation. High-level test generators often miss the low-level details, thus missing the detection of some gate-level faults. On the other hand, gate-level test generators...
Reversible logic synthesis has received considerable attention in the light of advances recently made in quantum computation. Implementation of a reversible circuit is envisaged by deploying several special types of quantum gates, such as k-CNOT. Although the classical stuck-at fault model is widely used for testing conventional CMOS circuits, new fault models, namely single missing-gate fault (SMGF),...
Communication in today's world is made efficient by digital data transmission. The digital communication employs parity generator at the source and parity checker at destination to ensure an error free transmission. This paper proposes the design of a 3-bit reversible even parity checker and generator using the basic reversible gates. The parity checker and generator circuit is designed using the...
The protection of the IGBT's in the case of an over-current or a short-circuit, respects the general methodology of a power electronic device protection. Usually, every power device is protected by its driver, which becomes a multifunctional circuit capable of assuring the driving signal, monitoring the operation state as well as providing its protection. In this paper we propose and realize a protection...
We show that the promise problem of distinguishing $n$-bit strings of hamming weights $1/2 +/- \Omega(1/\log^{d-1} n)$can be solved by explicit, randomized (unbounded-fan-in) $\poly(n)$-size depth-$d$ circuits with error $\le 1/3$, but cannot be solved by deterministic $\poly(n)$-size depth-$(d+1)$ circuits, for every $d \ge 2$; and the depth of both is tight. Previous results bounded the depth to...
Various applications in the modern world require DC supply. Some applications needs low DC voltage and some require considerably high DC voltage. We get AC supply and that needs to be converted to DC for these applications. In this paper AC - DC step up and step down converters without the use of bridge rectification is dealt. In step up converter, low AC voltage micro generators are used and the...
We propose a novel dual-mode neural stimulator circuit. For stimulation requiring small or medium amount of charge, the stimulator supplies a constant current to the stimulation load in the same way as any standard current-mode stimulator. For high-charge stimulation applications, the stimulator supplies a variable stimulus current, depending on the voltage available across the current generator circuit...
Quantum logic gate is a circuit, which performs a fixed unitary operation on selected qubits in a fixed period of time. The aim of this paper is to propose a simulator - Quantum Circuit Simulator (QCS) that simulates the quantum logic gates. This is a hardware-based simulator. Normally the quantum computers use quantum gates, which perform the arithmetic operations by means of Quantum Arithmetic And...
A Gaussian pulse generator is proposed for UWB impulse radio systems. The generator is probed in two modulation schemes (PP and BPSK) transmitting at 400 Mbps. The proposed modulators are coupled to a 50 ohms load. The Gaussian pulse generator has been designed and simulated in Mentor Graphics for a TSMC 0.18 um MMRF CMOS process with a power supply of +/-0.9 v.
A platform named USAT that integrates several gate-level and RTL satisfiability solvers is described. USAT has a unified circuit model that can represent both gate-level and RTL circuits. USAT integrates other solvers by translating between various circuit formats via the unified circuit model. USAT also includes a circuit generator that can generate RTL circuits with specific features specified by...
A new method for the generation of high quality sinusoidal signals is presented. Multi-bit binary signals are represented using uniformly weighted single bit-streams which can then be processed by digital logic. Building blocks useful for the construction of the sinusoidal generator are also presented. The bit-stream representation has the advantage of having the characteristics of a classical PWM...
This paper introduces a complete test package in VHDL that makes it possible to simulate faults and generate test patterns for a component during its design process. Different approaches on test applications can be combined and then be applied to combinational, sequential and scan-based circuits in a fully configurable and convenient environment. To reveal the capabilities of VHDL in test configurations,...
Switching regulator is used in many electronics devices because of its small size and low power consumption. Sawtooth wave is one of the important components of the switching regulator and determines the accuracy of the duty ratio of the switching regulator. When the sawtooth wave has fall time, the duty ratio has an error. In this paper, method to realize sawtooth wave generator which has slight...
We propose a built-in scheme for generating all patterns of a given deterministic test set T. The scheme is based on grouping the columns of T, so that in each group of columns the number ri of unique representatives (row subvectors) as well as their product R over all such groups is kept at a minimum. The representatives of each group (segment) are then generated by a small finite state machine (FSM)...
Present and future semiconductor technologies are characterized by increasing parameters variations as well as an increasing susceptibility to external disturbances. Transient errors during system operation are no longer restricted to memories but also affect random logic, and a robust design becomes mandatory to ensure a reliable system operation. Self-checking circuits rely on redundancy to detect...
A novel scheme for reducing the test application time in accumulator-based test-pattern generation is presented. The proposed scheme exhibits extremely low demand for hardware. It is based on a decoder whose inputs are driven by a very slow external tester. Experimental results on ISCAS benchmarks substantiate a test-time reduction of 75%-95% when compared to previously published test-set embedding...
The objective of using logic BIST for online and periodic testing is to identify defects, like opens, resulting from the wear and tear of the circuit. We have shown that existing test sets have a low coverage for open defects located in scan flip-flops, even though such defects may affect functional operation. Existing Logic BIST structures suffer from the same limitations. A novel Logic BIST architecture...
Soft errors caused by ionizing radiation have emerged as a major concern for current generation of CMOS technologies and the trend is expected to get worse. Soft error rate (SER) measurement, expressed as number of failures encountered per billion hours of device operation, is time consuming and involves significant test cost. The cost stems from having to connect a device-under-test to a tester for...
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