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A new low-power (LP) scan-based built-in self-test (BIST) technique is proposed based on weighted pseudorandom test pattern generation and reseeding. A new LP scan architecture is proposed, which supports both pseudorandom testing and deterministic BIST. During the pseudorandom testing phase, an LP weighted random test pattern generation scheme is proposed by disabling a part of scan chains. During...
Built-in self-repair (BISR) concept is widely utilized and proven by industry to increase the reliability of regular structures such as memory cores. The idea of using this concept in mostly irregular structures such as logic cores is quite new and represents a challenging task with many problems involved; e.g. the identification of regular parts in a logic core suitable for reconfiguration, excessive...
Distributed operation of microgrid architectures consists of energy management, power management, power electronics management, and fault detection and recovery. Centralized control of microgrids may be conceptually and practically infeasible due to questions of reliability and ownership. A Distributed Operating System architecture is proposed to manage power and computational resources within a smart...
Testing of high-speed Digital-to-Analog Converters (DACs) is a challenging task, as it requires large number of high-speed synchronized input signals with specific test patterns. To overcome this problem, we propose use of PRBS signals with an “Alternate-Bit-Tapping” technique and eye-diagram measurement as a solution to efficiently generate the test-vectors and test the DACs. This approach covers...
This paper considers the possibility of implementing low-cost hardware techniques which would allow to tolerate temporary faults in the datapaths of coarse-grained reconfigurable architectures (CGRAs). Our goal was to use less hardware overhead than commonly used duplication or triplication methods. The proposed technique relies on concurrent error detection by using residue code modulo 3 and re-execution...
Electrical distribution systems (EDS) are undergoing some significant changes at various scales and levels. These changes are triggered by several factors such as the event of distributed energy resources (DER) and the need to improve the quality of supply while achieving economical optima. Hence, several research initiatives, technological development and experiments have been launched worldwide...
Increasing complexity of interconnected electricity grids with a high integration level of dispersed generators leads that ldquobusiness as usualrdquo operating modes and regular devices in distribution networks are not efficient enough to ensure the centralized management of a large amount of information and high-level functionalities (advanced distribution automation-ADA) for future electricity...
Design and testing of analog and mixed-signal (AMS) circuits is often regarded as representing significant bottlenecks in system-on-chip (SOC) design. Testing the analog and mixed-signal circuitry of a mixed-signal IC has become a difficult task. This is due to the fact that most analog and mixed signal circuits are tested by its functionality, which is both time consuming and expensive. Hence the...
This demonstration presents an approach that facilitates variability implementation, management, and tracing from architectural modeling to implementation. A tool suite is provided that integrates aspect-oriented and model-driven software development into product line engineering.
Due to their reconfigurability and their high density of resources, SRAM-based FPGAs are more and more used in embedded systems. For some applications (Pay-TV,Banking, Telecommunication ...), a high level of security is needed. FPGAs are intrinsically sensitive to ionizing effects, such as light stimulation, and attackers can try to exploit faults injected in the downloaded configuration. Previous...
Cryptographic devices are recently implemented with different countermeasures against side channel attacks and fault analysis. Moreover, some usual testing techniques, such as scan chains, are not allowed or restricted for security requirements. In this paper, we analyze the impact that error detecting schemes have on the testability of an implementation of the advanced encryption standard, in particular...
The objective of using logic BIST for online and periodic testing is to identify defects, like opens, resulting from the wear and tear of the circuit. We have shown that existing test sets have a low coverage for open defects located in scan flip-flops, even though such defects may affect functional operation. Existing Logic BIST structures suffer from the same limitations. A novel Logic BIST architecture...
Soft errors caused by ionizing radiation have emerged as a major concern for current generation of CMOS technologies and the trend is expected to get worse. Soft error rate (SER) measurement, expressed as number of failures encountered per billion hours of device operation, is time consuming and involves significant test cost. The cost stems from having to connect a device-under-test to a tester for...
This paper describes a methodology for building a reliable internet core router that considers the vulnerability of its electronic components to single event upset (SEU). It begins with a set of meaningful system level metrics that can be related to product reliability requirements. A specification is then defined that can be effectively used during the system architecture, silicon and software design...
Memory built-in self test (MBIST) or as to it array built-in self test is an amazing piece of logic. Without any direct connection to the outside world, a very complex embedded memory can be tested efficiently, easily and less costly. Modeling and simulation of finite state machine (FSM) MBIST is presented in this paper. The design architecture is written in very high speed integrated circuit hardware...
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