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CMOS DRAMs which were first introduced commercially in the 256Kb DRAM generation have proven their advantages in power and performance, and are expected to be the future trend. In CMOS DRAMs, the half-VDD bitline sensing scheme — is widely used in the current generation of 1 Mb DRAMs. However, the half-VDD sensing scheme suffers a performance degradation as VDD is reduced. Starting with the 4 Mb DRAM...
A 1.2 V, 10 b, 40 MS/s pipelined ADC fabricated in 0.13µm one-poly eight-metal (1P8M) standard CMOS process with MIM capacitors is presented. This ADC used a novel low-variation on-resistance CMOS sampling switch to improve the nonlinear effect and a two-stage recycling folded-cascode (RFC) amplifier with hybrid frequency compensation for power saving and low voltage supply requirements. By implementing...
In this work a new structure of current mode min-max circuit using 0.18µm. CMOS standard technology is presented. It is based on cascode current mirror and enjoys 30 NMOS transistors. A 1.8(V) power supply is applied and simulation results are prepared using HSPICE software with level 49 parameters (BSIM3v3). It has noticeable advantages like 0.9 percent error in maximum input signal amplitude, 0...
A novel class-AB Flipped Voltage Follower is proposed, suitable for low-voltage low-power CMOS implementation in advanced technology nodes. Simulations have been performed using STMicroelectronics models for the 45nm technology. The Flipped Voltage Follower allows low output impedance and high linearity by means of a feedback loop. However, like the conventional common-drain voltage follower, it has...
This paper presents a high-speed and high-gain dynamic residue amplifier for two-stage SAR-assisted pipeline ADC. Parametric amplification technique is incorporated in the residue amplifier to enhance the gain, in order to meet the industrial requirements of the residue amplifier of an ADC with ENOB ≥ 10.5 bits. From simulations the proposed circuit has shown a gain of 22.05 dB and a power consumption...
In this work, the implementation of the PRESENT-80 block cipher in a 40nm CMOS technology, and its vulnerability to Side Channel Attacks Exploiting Static Power is investigated. In the last two decades, several countermeasures to thwart DPA/CPA attacks based on the exploitation of dynamic power consumption have been proposed. In particular, WDDL logic style is a gate-level countermeasure, to Power...
The possibility of recovering sensible information through the observation of dynamic power consumption of a cryptographic device is a critical issue in security applications. As it has been widely demonstrated in the literature, it is possible to reveal the secret keys of a cryptographic device exploiting the information leaked by the implementation through the power side channel. An on-chip, analog,...
A zero-crossing based amplifier whose power is scalable to a sampling frequency is presented. An inverter-based zero-crossing detector (ZCD) is proposed to consume no static power consumption compared with a conventional ZCD using a class-A based preamplifier. A common-mode feedback (CMFB) circuit is adopted to calibrate a variation of a ZCD threshold voltage due to supply voltage and temperature...
In this paper, a 10b 100-to-500 kS/s asynchronous SAR ADC is proposed and prototyped in 0.18 μm CMOS. The supply voltage is scaled down appropriately for different sampling speeds to minimize the power consumption. At a 0.5-V supply voltage and a 100 kS/s sampling rate, the ADC achieves a signal-to-noise and distortion ratio of 56.35 dB and consumes 424 nW, resultin g in a figure of merit of 7.9 fJ/conversion-step...
Many existing XOR-XNOR cells suffer from nonfull-swing outputs, high power consumption and low speed issues. In this paper, a new fast, full-swing and low-power XOR-XNOR cell, is presented. Simulation results in 90-nm CMOS technology show that the proposed circuit has rail to rail outputs Also, we have gained 11%–51%, 2%–19% and 18%–52% improvement in delay, power consumption and power-delay product...
Consider the structure of a self-oscillation power amplifier as a power line driver. Self-oscillation power amplifier was improved by the Class-D power amplifier. The traditional Class-D switching power amplifier is vulnerable to distortion limitation. Due to the non-linear continuous time nature of the self-oscillation, it possesses peculiar properties that enable the construction of a highly linear,...
Filter-banks based on a gm-C topology are popular in acoustic sensor systems targeting spectral analysis. Their benefits lie in a very low power consumption and center-frequency scalability through gm-tuning to cover the audio frequency range. However the linear signal swing at the output of the filter is limited due to the inherent non-linearity of the input transistors in a differential pair. This...
The depth information is actively utilized for many applications such as mobile gesture user interface (UI). However, the previous stereo vision systems are unsuitable for the mobile gesture UI due to the long latency and the high-power consumption of external image sensor in embedded environments. In this paper, we propose a CMOS image sensor-based real-time stereo matching accelerator with low power...
This paper investigates the substitution of CMOS or near-threshold CMOS with Charge Recovery Logic (CRL) in applications where energy is thermally harvested. By doing so, it is possible to eliminate the bulky DC/DC stage needed to provide the supply voltage for CMOS operation. Instead, a simple LC-tank oscillator is used to generate a power-clock suitable for CRL operation. Simulation results of a...
A high-speed low-power 1:16 demultiplexer with a novel symmetrical-edge-delay sense amplifier is presented in this paper. The traditional Sense-Amplifier-Based Flip-Flop (SAFF) has asymmetric rising and falling edges with the fact that the falling edge lags the rising edge the time of a gate delay, which has become a bottleneck of speed. In order to overcome the problem of nonsymmetry of output data...
In this paper, a hybird adaptive Coordinate Rotation Digital Computer (HA-CORDIC) has implemented in 65nm Silicon On Thin Buried oxide (SOTB) CMOS technology. In the HA-CORDIC implementation, the adaptive algorithm is utilized for reducing the iteration of CORDIC algorithm. In comparison with other floating-point CORDIC designs, the latency of our proposed scheme is lower. It spends only 12, 20, and...
In this Paper, we propose a new method for safe electrical neural stimulation. Current mode digital-to-analog converters are used to generate the cathodic and the anodic stimulation phases. A sample-and-hold and a window comparator circuit are used to compare the voltage of the electrode and the tissue with a target value within a safe voltage range of −50 mV to +50 mV. When the electrode voltage...
This paper reports a monolithic device integrating a CMOS analog front-end and an array of 192 MR sensors for biomolecular recognition detection. Innovative CMOS building blocks (i.e. current source, multiplexers and pre-amplifier) were designed targeting a negligible noise when compared with the MR sensors noise and a low power consumption. The CMOS front-end was fabricated using AMS 0.35 μm technology...
Resistive (or memristive) devices, including resistive switching memory (RRAM), phase change memory (PCM) an spin-transfer torque memory (STTRAM), are strong candidates for future high-density memory, embedded memory and storage class memory. The availability of resistive-device technology in the industry would pave the way for several other applications in advanced computing, such as neuromorphic...
Ten years ago, at 90 nanometers, EDA was challenged and deemed inadequate in dealing with increasing complexity, power consumption, and sub-wavelength lithography, thus harming the progress of mobile phones. Today, at 10 nanometers, integration capacity has increased by two orders of magnitude, power consumption has been successfully “tamed”, and 193 nanometer immersion lithography is still relied...
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