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In this work, a simple electric circuit model for the evaluation of the impact of vias (inter-metallic vertical connections) in resonant rotary traveling wave oscillator (RTWO) is proposed. A test structure was designed to quantify the degradation on the signal integrity of RTWOs caused by these vias. The test structure and the RTWO were designed according to the rules of the 130 nm commercial mixed...
The single event transients (SETs) are a common source of malfunction in nano-scale CMOS integrated circuits. For this reason, evaluation of the SET effects and application of appropriate measures for their mitigation are fundamental tasks in the design of advanced radiation hardened integrated circuits. In general, SET analysis is based on the multi-scale modeling and simulation approach comprising...
In this paper, performance degradations of passive microwave components induced by deviations of metalstack dimensions in a 65 nm CMOS technology are presented. Customarily, on-chip passive microwave components use special technology options which evacuate large areas from metal fillers in order to decrease eddy-current losses. An issue of interest is the influence of metal filler absence on the dimensions...
This paper presents a study of passive Dickson based envelope detectors operating in the quadratic small signal regime, specifically intended to be used in RF front end of sensing units of IoE sensor nodes. Critical parameters such as open-circuit voltage sensitivity (OCVS), charge time, input impedance, and output noise are studied and simplified circuit models are proposed to predict the behavior...
This paper investigates the use of stacked depletion-mode n-channel MOSFET (D-MOS) for RF switch applications. Compared to the commonly used enhancement-mode MOSFET (E-MOS), the D-MOS transistor offers a significant reduction in on-state resistance (RON) and off-state capacitance (COFF) simultaneously and an excellent figure of merit (RonX Coff) of 134fs (roughly 3X improvement) can be achieved. With...
This paper deals with the implementation of low voltage, energy efficient and high speed 1-bit Full Adder (FA) cell in pass transistor (PT) logic by using 20 nm compact model parameters. The existing full adder with pass transistor logic suffers from a drawback of replication of full swing in sum and carry outputs and voltage step existed in both the outputs at low to high transition. These will be...
In this work a new structure of current mode min-max circuit using 0.18µm. CMOS standard technology is presented. It is based on cascode current mirror and enjoys 30 NMOS transistors. A 1.8(V) power supply is applied and simulation results are prepared using HSPICE software with level 49 parameters (BSIM3v3). It has noticeable advantages like 0.9 percent error in maximum input signal amplitude, 0...
In this paper a Reliability-AwaRE (RARE) method based on the gm/ID-methodology is presented which allows designers of integrated analog circuits to consider process as well as environmental variations and aging effects already at early design stages. The proposed method makes aging simulations on system level superfluous by utilizing a stochastic Look-Up table. The stochastic LUT contains simulated...
This paper presents a 124 to 184 GHz single-ended amplifier designed in 28-nm FDSOI CMOS technology. The amplifier consists of four common-source gain stages and broadband matching networks for input, output and inter-stage matching employing slow-wave shielded co-planar waveguides. Having a total power consumption of 31 mW, the amplifier achieves a peak gain of 10.1 dB at 167 GHz and a 3-dB bandwidth...
This paper presents a dual path Nuclear Magnetic Resonance (NMR) receiver dedicated to low cost NMR bio-molecular spectroscopy. Herein we present the design and implementation of CMOS based NMR receiver consisting of an integrated circuit (IC) incorporated with four mini-Coils for NMR exciting and recording purposes. The proposed 21 MHz CMOS receiver consists of differential low-noise amplifiers (LNAs),...
In this paper, we present a class D power amplifier (PA) design in 28 nm CMOS for a multilevel outphasing transmitter. For increased output power, the design consists of eight unit PAs with cascoded output stages. In order to improve back-off efficiency from conventional outphasing, the PAs are switched on and off in pairs for different amplitude levels, which is challenging to implement with cascoded...
It has been made clear that the presence of hot carriers triggers a series of physical processes that affects the FD-SOI and FinFET device characteristics under normal circuit operation. These effects cumulatively build up over prolonged periods, causing the circuit to age with time, resulting in performance degradations that may eventually lead to circuit failure. In this paper we tackle with the...
In this paper an analog cellular neural network is proposed with application in physical unclonable function design. Dynamical behavior of the circuit and its high sensitivity to the process variation can be exploited in a challenge-response security system. The proposed circuit can be used as unclonable core module in the secure systems for applications such as device identification/authentication...
We present a low-cost, portable electrochemical analysis system using impedimetric measurements rather than more commonly used potentiometric techniques. The presented impedance spectroscopy (impedimetric) technique uses a small perturbation to obtain a linearized response without affecting the composition of the sample as opposed to cyclic voltammetry (potentiometric) which repeatedly reduces and...
A substrate coupling analysis and simulation flow for high frequency CMOS system on chip design is presented. It's a straightforward method that can be directly adopted by designers as it only requires commercial design tools. Full chip level simulation including substrate, interconnect parasitics and package is provided in any stage of the design process. A 5 GHz CMOS LNA in the presence of an 88...
Although QCA (Quantum-dot Cellular Automata) is a promising nanotechnology to replace CMOS (Complementary Metal-Oxide-Semiconductor), it has several known reliability problems. Consequently, the design of robust QCA circuits is a mandatory step towards the consolidation of this new technology. This paper presents a novel methodology for error analysis of QCA circuits based on deterministic and random...
We present MUX based programmable logic circuits built from newly proposed compact and efficient designs of combinational logic gate. These are enabled by reconfigurable Schottky barrier nanowire transistors with multiple independent gates, which can be dynamically switched between p- and n-type functionality. It will be shown that a single device can be used to replace paths of several transistors...
Multiplier is one of the major hardware circuits of microprocessor and high performance systems such as digital signal processor; FIR filters, processing operations like Convolution, Cross Correlation, and auto-correlation of discrete signals, digital Image processing applications such as edge detection etc. The major design constraint of multiplier is speed which is affected due to propagation delay...
In this paper, the design of a RF MEMS oscillator on a silicon-ceramic composite substrate using a high-Q Lamb-wave resonator as frequency-selective device is described. The MEMS resonator is designed on a 1.8 µm thick piezoelectric AlN layer, deposited on silicon using thin-film processes. The finite-element simulation results of the resonator structure are presented, and the derivation of the electrical...
Quantum-dot Cellular Automata (QCA), a transistor-less paradigm is a compeer to the existing Complementary metal Oxide Semiconductor (CMOS) technology. The existing CMOS technology has to be mapped to quantum dot paradigm to create QCA structures that can be used to perform all the logic operations which are currently performed by the existing technology. Simple QCA structures that perform all adding...
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