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This paper provides a method for direct detection time-of-flight (TOF) laser ranging system based on time delay estimation to get higher precision than conventional ranging systems. Restricted by the conversion rate of Analog-to-Digital (ADC) CMOS chip while the laser echo signal is so narrow, the precision of the laser ranging system is restricted no more than the ADC sampling period. As this problem...
This paper presents a 4bit SAR ADC for ultra-low energy radios. It is not obvious to maintain good power-efficiency for low resolution, low data rate ADCs given fixed overhead and scaling limitations. Nevertheless, an excellent FOM of 25fJ/conversion-step is achieved by using a dedicated capacitor implementation, asynchronous dynamic logic, an optimized layout and a reduced power supply. The prototype...
Complementary metal oxide semiconductor (CMOS) image sensors are more compatible than charge coupled devices (CCDs) for lab-on-a-chip platforms due to their inherited advantages. However, without the noise reduction circuits, CMOS technology wouldn't be able to compete with CCDs. Today, correlated double sampling circuits (CCDs) are used in all CMOS imagers in order to remove the reset noise and the...
A 1.2V 10bit 83MS/s pipeline ADC implemented in 130nm CMOS Technology is described with practical design techniques and considerations. Emphasis was placed on noise analysis and capacitance optimization, which helps to reduce both die area and power consumption. Design experiences of operational amplifier, comparator and switches were also shared. This design achieves INL and DNL of +0.65/-0.53LSB...
A new kind of differential comparator is presented. A differential difference amplifier circuit is used to compare analog input signal and reference voltage. The experimental results show that the comparator improves speed and power performances compared with traditional comparators. The comparator is implemented in SMIC0.18 CMOS process, consumes 0.9 mW, and has a layout size of 508 μm2.
We present the design of an analog-to-information (A2I) converter consisting of parallel analog processing channels, whose output is sampled by traditional analog-to-digital converters (ADCs). The architecture employs a reconfigurable analog front-end that modulates the signal of interest with a high-speed digital chipping sequence and integrates the result prior to sampling at a low rate. This front-end...
We present a bio-inspired readout integrated circuit (ROIC) for visible and infrared image sensors. At the system level, the architecture relies on an event based readout scheme where only pixels within a programmable range of photon flux rates are output. At the pixel level, a one bit oversampled analog-to-digital converter together with a decimator allows for the quantization of signals up to 26...
A new switch control method for a capacitive DAC architecture has been presented. This has been implemented to make a successive approximation register (SAR) ADC more energy efficient. By splitting the capacitor array into two equal halves and using a unity gain buffer, the proposed architecture reduces the switching energy by 97 percent compared to the conventional switching method. The proposed...
A novel low-power successive approximation register is proposed. The new register is based on gating the clock when there is no data switching activity. It operates with fewer transistors and no redundant transitions which makes it suitable for low power applications. The proposed register consisting of 14 bits has been designed up to the layout level with 1V power supply in 90nm CMOS technology and...
Multi-electrode array devices are widely considered for sensing a large amount of neural data in implantable applications. In such systems power and area are playing most important roll in design and implementation. This paper presents a low power, variable bits and small area analog to digital converter (ADC) for biopotential and neural signals-recording applications. This work has been simulated...
Successive approximation analog-to-digital converters are very attractive to power-constrained applications due to the topology inherent energy efficiency. This converter architecture most often relies on digital controller circuit to guide the conversion algorithm, and this controller is reported to have an important impact on the overall power consumption, sometimes demanding roughly half the total...
The performance of data converters has been pushed relentlessly over the years, leveraging advancements in scaling and design techniques that exploit the high density and speed of modern process technology. However, most of the underlying architectures in use today were conceived decades ago, and are nowadays regarded as fundamental in their nature. Were these architectures viewed as fundamental,...
The successive-approximation (SA) algorithm is traditionally used for low bandwidth applications because it requires n clock cycles or more to obtain n-bit resolution. However, the use of modern nanometer CMOS technologies and special design solutions overcome the speed limit, enabling conversion rates in the hundreds of MHz with very low power consumptions. This design uses the successive-approximation...
Trends in cable TV reception for data and video require simultaneous capture of many channels, e.g., 16, arbitrary located in the 48-to-1002MHz TV band. The challenges of integrating more than two zero-IF tuners on a single die could be simplified with a low-power 10b ADC that can digitize the entire TV band and be suitable for integration with baseband DSP. This work presents a 64χ inter leaved 2...
In this paper, a prototype delta-sigma ADC is implemented in a 0.18μm 2P5M CMOS process. The input signal sampling capacitors are shared with the front-end DAC capacitors. The sampling frequency is 50MHz and oversampling ratio is 24. The out-of-band peaking is deliberately set to help the stability and to allow larger input signals to be processed by the loop. This modulator achieves 78.2dB peak SNDR...
Terahertz and mm-Wave-based imagers have recently gained interest for imaging in security screening and bio-imaging applications. For these applications to become practical, the core pixel circuits employed in an imaging array must meet challenging constraints that originate from the system level design and the needs of constructing large array structures on-chip. The most critical of these constraints...
The high channel count of many modern communication systems increasingly requires high-performance ADCs that consume very little power. The 16b pipeline ADC described here achieves 77.6dBFS SNR, 77.6dBFS SNDR and 95dBc SFDR at 80MS/S with a 10MHz input. With a 200MHz input, the ADC achieves 71.0dBFS SNR, 69.4dBFS SNDR and 81dBc SFDR. The complete ADC including reference, clock, and digital circuitry...
In this paper, a high-speed continuous-time (CT) ΔΣ ADC topology is proposed that absorbs the pole normally caused by the quantizer's input capacitance, while a local feedback loop compensates for the quantizer's excess delay. These meas ures allow a high-resolution multi-bit ΔΣ ADC to operate at GHz sampling rates. The bandwidth of this CMOS ΔΣ ADC is 6x wider than the state-of-the-art. Compared...
This work describes a 9bit 200MSPS 0.18μm CMOS process four-stage parallel pipeline ADC with 2.5 bit per stage. Primary objective of the design has been to make a trade-off between power consumption and resolution while keeping the sampling rate high. The parallel-pipeline architecture was best fit for such requirements. A new sub-ADC scheme has been introduced here to remove possible switch generated...
ADC-based receivers allow for extensive equalization in the digital domain and therefore can easily compensate for channel loss at higher data rates. Digital equalization can be implemented as an FFE or DFE. An adaptive FFE is straight forward to implement, as it relies on magnitudes only (not phases) of the blind samples, however, it enhances the quantization noise of the ADC. A DFE has better noise...
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