The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Most prior work on hardware reliability make use of module (spatial) redundancy or time redundancy. In the first case, these methods assume that each module is exactly the same. Multiple module replicas implementing the same logic function are executed in different hardware channels and a voting scheme detects if the outputs match or not. In the second case, they re-compute the result using the same...
Complex computational systems can experience undetected faults that produce incorrect outputs. However, error measures can be adopted to quantify these incorrect results and evaluate computational robustness. This paper offers an approach to assessing the worst case scalable robustness (WCSR) of an algorithm paired with an error measure, as well as the i.i.d. average case scalable robustness (ACSRiid)...
A Self-rePAiring spiking Neural NEtwoRk (SPANNER) hardware architecture is presented in this paper. It is based on a software model of an astrocyte-neuron network which previously demonstrated the ability to self-detect faults and self-repair autonomously. Experimental results in this paper show that when faults occur at the synapse, remaining healthy synapses of the same neuron are enhanced by the...
Stochastic computing (SC) [1] has received attention recently as a paradigm to improve energy efficiency and fault tolerance. SC uses hardware-generated random bitstreams to represent numbers in the [0:1] range - the number represented is the probability of a bit in the stream being logic-1. The generation of random bitstreams is typically done using linear-feedback shift register (LFSR)-based random...
Several approaches to design of fault-secure or/and fault-tolerant digital finite input response (FIR) filters with varying fault coverage and hardware efficiency have been proposed. However, no specific implementations in modern nanometric technologies using error detecting codes like residue codes or parity codes has been reported yet. In this paper, we will study design of fault-secure multipliersaccumulators...
This paper presents the implementation of the error recovery scheme from temporary faults, applicable for datapaths of coarse-grained reconfigurable architectures. We have chosen the DART architecture as a vehicle to study various aspects related to implementation of the instruction retry in a complex highly parallel reconfigurable system. Synthesis results have confirmed the time, hardware, and power...
This paper presents a design methodology for multiple bit error detection and correction in Galois field arithmetic circuits such as the bit parallel polynomial basis (PB) multipliers over GF(2m). These multipliers are crucial in most of the cryptographic hardware designs and hence it is essential to ensure that they are not vulnerable to security threats. Security threats arising from injected soft...
This paper considers the possibility of implementing low-cost hardware techniques which would allow to tolerate temporary faults in the datapaths of coarse-grained reconfigurable architectures (CGRAs). Our goal was to use less hardware overhead than commonly used duplication or triplication methods. The proposed technique relies on concurrent error detection by using residue code modulo 3 and re-execution...
This article proposes a method which reduces delay and area in EDAC circuits. A SEC-DED Hsiao code (39,32) and a DEC systematic (1 6, 8) code used for the hardware implementation of EDAC, are discussed and compared. Two codes are all proposed by the authors in earlier paper. In terms of parity-check matrix of these codes, this article presents a low-cost generation method of check bits. Simulation...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.