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This paper presents 3D IC design of a fully integrated four-phase buck converter. The control circuit was implemented in the TSMC 0.18μm CMOS Mixed Signal RF General Purpose MiM Al 1P6M 1.8 & 3.3V process while the passive components were implemented in the tMt Glass Substrate Integrated Passive Device (IPD) Process, and then these two dies are stacked. Thus, a high output loading current can...
A CMOS true time delay (TTD) chain operating from 1 GHz to 21 GHz is presented for ultra-broadband phased array systems. An eight-stage trombone configuration is employed to provide 3-bit tuning capability. The second order all pass network (APN) is used to construct the gate line and drain line. The adoption of the APN increases the achievable delay while maintaining a compact size. The larger shunt...
Ultra wideband radar implementations for millimeter-/microwave operation are emerging in CMOS requiring high bandwidth. A distributed amplifier (DA) topology for use as low-noise amplifier (LNA) in nanometer CMOS, is explored in this paper. Important modifications like direct termination is beneficial both in area and gain linearity. A 5-stage amplifier provides a −3dB bandwidth of 36.5GHz and a S...
This paper presents a complete 50–64 Gb/s serializing transmitter including a 4-tap equalizer. The serializer is power-optimized by using a direct 4:1 multiplexer (MUX) at the final stage with a novel 4:1 MUX circuit design. In addition, an LC-based FFE structure that eliminates the need of multiple MUXs is proposed. The FFE improves the bandwidth of the delay line and the output combiner by applying...
A 100 Gb/s CMOS transimpedance amplifier (TIA) for high speed optical communication receivers is presented in this paper. The TIA is based on a differential architecture and composed of a regulated cascode block and a differential amplifier with active feedback. It adopts peaking inductors and a capacitive degeneration scheme to increase the bandwidth. The TIA is designed and laid out in CMOS 65 nm...
The design of 5–9 GHz, two stages CMOS power amplifier (PA) for Ultra-wideband (UWB) is presented in this paper. Post-layout simulation results indicated a power gain S21 of 16± 0.5dB, an input return loss S11 less than −4 dB and an output return loss S22 less than −5 dB over the frequency range of interest. Source-pull contours were used to design the inter stage matching of the PA. The proposed...
Three CMOS integrated circuits are presented that utilize metamaterial composite right/left handed (CRLH) transmission lines (TLs) for tunable zero insertion phase at 30 GHz. Initially, two passive fixed TL structures are realized followed by an active design using accumulation-mode NMOS varactors. An tunable insertion from -9deg to +27deg can be observed. Results suggest the possibility of zero,...
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