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Elastic systems operate in a dataflow-like mode using a distributed scalable control and tolerating variable-latency computations. At the same time, multithreading increases the utilization of processing units and hides the latency of each operation by time-multiplexing operations of different threads in the datapath. This paper proposes a model to unify multithreading and elasticity. A new multithreaded...
Pipeline requires both low latency and high throughput. Synchronous pipeline achieves a near optimized throughput but suffers from the worst-case computation delay. Meanwhile, asynchronous pipeline keeps an optimized computation delay but suffers from the low throughput. In this paper, we present dual control path (DCP), a new structure of four-phase handshake asynchronous control path, to improve...
Distributed key-value stores employed in data centers treat each key-value pair as a shared memory register. For fault-tolerance and performance, each key-value pair is replicated. Various models exist for the consistency of data amongst the replicas. While atomic consistency, also known as linearizability, provides the strongest form of consistency for read and write operations, various key-value...
In a synchronous digital system, the activity of the clock signal is a major energy consumer. It is responsible for 15% to 45% of the total consumed energy. Once reducing the activity of the clock signal, it is possible not only a reduction of the considered energy, but also a reduction of clock skew problems and electromagnetic iteration. An interesting strategy to achieve this goal is to design...
A new asynchronous interconnection network is introduced for globally-asynchronous locally-synchronous (GALS)chip multiprocessors. The network eliminates the need for global clock distribution, and can interface multiple synchronous timing domains operating at unrelated clock rates. In particular, two new highly-concurrent asynchronous components are introduced which provide simple routing and arbitration/merge...
Network-on-chip architectures partitioned into several Voltage/Frequency Islands (VFIs) have been proposed to alleviate problems related to integration, excessive energy consumption and clock distribution. The architecture is composed of synchronous switches that communicate with each other using bi-synchronous FIFOs. However, these FIFOs are not needed if adjacent switches belong to the same clock...
Originally the Latency insensitive protocols (LIP) were invented to make a system elastic to the interconnect latencies using handshaking signals such as `valid' and `stall'. These require extra signals leading to area overhead and may affect throughput of the system. To optimize away some of these overheads, scheduled LIPs were proposed which replaced the complex handshake control blocks by a central...
Multiprocessor system-on-chip design (MPSoC) is becoming a regular feature of the embedded systems. Shared-bus systems hold many advantages, but they do not scale. Network on chip (NoC) offers a promising solution to the scalability problem by enhancing the topology design. However, standard NoCs are only scalable within a chip. To be able to build infinitely scalable structures, a method to enhance...
Networks-on-chip (NoCs) have emerged as a new design paradigm to implement MPSoCs that competes with the standard bus approach. They offer more scalability, flexibility, and bandwidth. Nevertheless, FPGA manufacturers still use the bus paradigm in their development frameworks. In this paper, we study the complexity and performances of a FPGA implementation for a crossbar NoC. We propose a generic...
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