The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Multi-Level Processing reduces the cost of synchronization overhead with an upper level processor for taking control and issuing the right to use shared data and to enter critical sections directly to each of lower level processors at processor speed. The instruction registers of lower level parallel processors are mapped to the data memory of upper level processor. The upper level processor has the...
Godson-T is a research many-core processor designed for parallel scientific computing that delivers efficient performance and flexible programmability simultaneously. It also has many features to achieve high efficiency for on-chip resource utilization, such as a region-based cache coherence protocol, data transfer agents, and hardware-supported synchronization mechanisms. Finally, it also features...
Computing circuits that implement logically irreversible operations unavoidably dissipate heat. The resulting dissipative costs, while insignificant in CMOS technology, may be dominant or even prohibitive in some dense, high speed post-CMOS nanocomputing approaches. This motivates determination of lower bounds on the dissipative cost of computation that can be applied to concrete nanocomputing technology...
This paper presents a novel, high performance and low cost execution architecture for the system level GALS programming language SystemJ, which extends Java with synchronous reactive features present in Esterel and asynchronous constructs of CSP (Communicating Sequential Processes). The new architecture is based on JOP (Java Optimized Processor), which is a hardware implementation of the Java Virtual...
Along with the developments of VLSI technologies, the entire industrial control computer system can be integrated into one chip, so called industrial control SoC. The serial and parallel interface plays an important role in the communications between industrial control system and the peripherals. The paper discusses the design of the serial and parallel protocol communication controller of industrial...
Nowadays, communication protocols are used in safety-critical automotive applications. In these applications, fault tolerance is a main requirement and the existence of single points of failure is a serious threat to system failures. Among the communication protocols, FlexRay is expected to become the communication backbone for future automotive systems. In this paper, we identify single points of...
According to the specified standard of airborne Photogrammetry, digital airborne cameras must have higher performance than ordinary civil cameras, which must shoot with shorter time interval and will generate huge data stream. In this paper, a digital airborne camera is designed and implemented in a single FPGA chip as a SOPC approach. The functions of image acquisition, storage and display are implemented...
This paper describes a method of synthesising asynchronous circuits based on the Handshake Circuit paradigm but employing a data-driven, rather than the control-driven, style. This approach attempts to combine the performance advantages of data-driven asynchronous design styles with the handshake circuit style of construction. The integration into the existing Balsa design flow of a compiler for descriptions...
The complexity of integrated-circuit chips produced today makes it feasible to build inexpensive, special-purpose subsystems that rapidly solve sophisticated problems on behalf of a general-purpose host computer. This paper contributes to the design methodology of efficient VLSI algorithms. We present a transformation that converts synchronous systems into more time-efficient, systolic implementations...
We introduce a network of processing elements, the cube-connected-cycles (CCC), complying with the present technological constraints of VLSI design. By combining the principles of parallelism and pipelining, the CCC can emulate the cube-connected machine with no significant degradation of performance but with a much more compact structure. We describe in detail how to program the CCC for efficiently...
This paper presents an extension of the basic concepts established by Robert McNaughton and David Muller in the field of asynchronous feedback networks. The ideas developed herein are the results of adapting common logical functions in a manner that simplifies the overall design of asynchronous systems. The prime objecttive is to overcome a weakness common to both of the aforementioned concepts, that...
The inherent problems of data transmission in a strictly feedforward line have been discussed in the literature. In such a line, where the stored data are indexed forward by control pulses moving in a direction away from the data source, if time variations exist in the delays of successive stages then there is always a nonzero probability that two successive control pulses will eventually appear at...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.