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FPGAs have grown considerably in the past years. In the meantime it is possible to implement several soft-core processors in one FPGA. This enables considerable parallelism for the developer. Unfortunately, most application code is still available in sequential form. Thus, in this contribution we present a tool that enables the automated transformation of an application into a streaming pipeline using...
The paper depicts the RTL (Register Transfer Level) description of Binary Multiplier and Binary Divider. The descriptions are synchronized to the operating clock of the microprocessor. The major operations that get a highlight in this paper is that the multiplier and divider are synthesizable. VHDL (Very High Specific Integrated Circuit — Hardware Description Language) is the language of construct...
This paper describes a substation avalanche test system which is based on B code. The system supports simultaneous operation of multiple remote signaling and can ensure the synchronization and accuracy of time's movement. Using platform of ARM9 hardware and embedded operating systems, the system has lots of feature, such as high integration, small size and stable. The host computer can operate the...
The Niagara2 CMT system-on-chip incorporates many design-for-test features to achieve high test coverage for both arrays and logic. All the arrays are tested using memory built-in-self-test. This is supplemented with scan-based testing. Logic is tested with standard ATPG for slow-speed defects and extensive use of transition test, along with logic built-in-self-test for the SPARC cores, for at-speed...
For several decades, the output from semiconductor manufacturers has been high volume products with process optimisation being continued throughout the lifetime of the product to ensure a satisfactory yield. However, product lifetimes are continually shrinking to keep pace with market demands. Furthermore there is an increase in dasiafoundrypsila business where product volumes are low; consequently...
A high bandwidth critical path monitor (1 sample/ cycle at 4-5 GHz) capable of providing real-time timing margin information to a variable voltage/frequency scaling control loop is described. The critical path monitor tracks the critical path delay to within 1 FO2 inverter delay with a standard deviation less than 3 FO2 delays over process, voltage, temperature, and workload. The CPM is sensitive...
The Sequoia computer is a tightly coupled multiprocessor that avoids most of the fault-tolerance disadvantages of tight coupling by using a fault-tolerant hardware-design approach. An overview is give of how the hardware architecture and operating system (OS) work together to provide a high degree of fault tolerance with good system performance. A description of hardware is followed by a discussion...
The complexity of integrated-circuit chips produced today makes it feasible to build inexpensive, special-purpose subsystems that rapidly solve sophisticated problems on behalf of a general-purpose host computer. This paper contributes to the design methodology of efficient VLSI algorithms. We present a transformation that converts synchronous systems into more time-efficient, systolic implementations...
We describe a formal theory of the total correctness of parallel programs, including such heretofore theoretically incomplete properties as safety from deadlock and starvation. We present a consistent and complete set of proof rules for the total correctness of parallel programs expressed in nondeterministic form. The proof of consistency and completeness is novel in that we show that the weakest...
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