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In the context of industrial designs, circuits are based on many IPs defined on their own clock domain. It leads to globally asynchronous locally synchronous designs. The transmission of data between clock domains must be carefully verified to avoid metastability, inconsistency and data loss. EDA tools propose a strategy based on a minimal detection of a synchronizer structure. Conversely, in this...
In the context of industrial size circuits, the interconnection of many blocks from many sources lead to globally asynchronous locally synchronous designs. The transmission of information between clock domains requires complex synchronizers, the correctness of which must be thoroughly verified. Current EDA tools are able to recognize predefined synchronizing modules, but fail to identify custom synchronizers...
Collecting highly accurate scientific measurements asks for highest data quality and yield. But, satisfying these requirements is non-trivial, when considering phenomena common to wireless sensing systems such as clock drift, packet duplicates, packet loss and device reboots. Previous experience shows that these problems have not been resolved sufficiently by system design. In this paper, we introduce...
One of the main purposes to use SystemC in system development is to perform system-level verification in the early design stage. However, simulation is still by far the only available solution for the high-level SystemC design verification. Nonetheless, traditional formal verification techniques, which rely on the translation of designs under verification to logic netlists, cannot be easily adopted...
This paper proposes a systematic composition method for supporting both top-down and bottom-up approaches within the same frame. The method composes behavioral models of unit(abstract) components with respect to the services to be provided by the abstract component after the composition. Adapted from the standard operations in process algebra, two types of abstract techniques, synchronized abstraction...
Compared with traditional verification method for structural correctness of model based on Petri net graph reduction, The method in text adds reduction methods for the general iterative structure and the adjacent structure. A method for converting the non-freely chosen WF-net model into the freely chosen WF-net model in equivalence is put forward, therefore realizing the verification for all kinds...
In this paper, we present automated formal verification of the DHCP Failover protocol. We conduct bounded model-checking for the protocol using Timeout Order Abstraction (TO-Abstraction), a technique to abstract a given timed model in a certain sub-class of loosely synchronized real-time distributed systems into an untimed model. A resulting untimed model from TO-abstraction is a finite state machine,...
Existing reachability analysis techniques are easy to fail when applied to large compositional linear hybrid systems, since their memory usages rise up quickly with the increase of systems' size. To address this problem, we propose a tool BACH 2 that adopts a path-oriented method for bounded reachability analysis of compositional linear hybrid systems. For each component, a path is selected and all...
In this paper we introduce a syntax and semantics for capturing complex relational behaviour commonly found in natural language system requirements. The syntax is an extension of Behaviour Trees, a modelling notation used for capturing user requirements from natural language in a structured way. The underlying semantics of the extended notation is based on that of relational databases, thereby allowing...
Modern device trends present greater challenges to design [1] because many of them integrate continuous and discrete sub-systems and therefore their design involves specific global modeling and validation approaches. This paper proposes the operational semantics for rollback-based synchronization model that may be used in continuous/discrete systems simulation. The paper also addresses the formal...
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