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Development of technologies in bioinformatics resulted into many folds growth of biological data that led to the research for accelerated solutions in various domains of computational bioinformatics. String matching is one of the most widely performed tasks at various stages of computational pipeline and it needs an accelerated and reconfigurable methodology for implementation. In this paper we present...
In this paper we propose an on-the-fly reconfigurable hardware-software codesign based reconfigurable solution for real-time protein identification. Reconfigurable string matching is performed in the disciplines of protein identification and biomarkers discovery. With the generation of plethora of sequenced data and number of biomarkers for several diseases, it is becoming necessary to have an accelerated...
In this paper, we introduce a course centered around MIPSfpga, an unobfuscated commercial MIPS soft-core processor made available by Imagination Technologies for academic purposes. The course focuses on hands-on learning that emphasizes System on Chip (SoC) design and hardware-software codesign. Students first study MIPS computer architecture and microarchitecture and then learn and experiment with...
The growing complexity and diversity of embedded systems–combined with continuing demands for higher performance and lower power consumption–places increasing pressure on embedded platforms designers. The target of the ERA project is to offer a holistic, multi-dimensional methodology to address these problems in a unified framework exploiting the inter- and intra-synergism between the reconfigurable...
Traditionally, common processor augmentation solutions have involved the addition of coprocessors or the datapath integration of custom instructions within extensible processors as Instruction Set Extensions (ISE). Rarely is the hybrid option of using both techniques explored. Much research already exists concerning the identification and selection of custom hardware blocks from hardware/software...
The Software/Hardware Implementation and Research Architecture (SHIRA) is a C to hardware toolchain developed by the Computer Architecture Research Group (CARG) of the University of Ottawa. The framework and algorithms to generate the hardware from an Intermediate Representation (IR) of the C code is needed. This paper presents the conceiving, design, and development of a module that generates the...
Customized application-specific processors called ASIPs are becoming commonplace in contemporary embedded system designs. Neural networks are an interesting application for which an ASIP can be tailored to increase performance, lower power consumption and/or increase throughput. Here, both the bidirectional associative memory and hopfield auto-associative memory networks are run through an automated...
This paper presents a QEMU and SystemC-based virtual platform that is capable of hardware modeling using TLM-2.0 interface. The proposed virtual platform is not only capable of running an operating system, but it is also capable of using such an interface to connect hardware models, such as the instruction set simulator to a bus model. We verify the functionality of such a platform by using it to...
HW/SW Co-designed systems rely on dynamic binary translation and optimizations for efficient execution of binary code. Due to memory ordering properties and other architectural constraints, most binary optimizations are applied to regions of code that are atomically executed. To ensure that the underlying hardware has enough speculative resources to execute the whole atomic region, these systems typically...
The performance of a wireless system depends on the wireless channel as well as the algorithms used in the transceiver pipelines. Because physical phenomena affect transceiver pipelines in difficult to predict ways, detailed simulation of the entire transceiver system is needed to evaluate even a single processing block. Further, some protocol validations require simulation of rare events (say, 1...
Multi-core system is becoming the next generation embedded design platform. Heterogeneous and homogeneous processor cores integrated in Multiple Instruction Multiple Data (MIMD) System-on-a-Chip (SoC) to provide complex services, e.g. smart phones, is coming up in the horizon. However, distributed programming is a difficult problem in such systems. Today, only in very few MIMD SoC designs we can find...
In this paper we have explored different possibilities for partitioning the tasks between hardware, software and locality for the implementation of the vision sensor node, used in wireless vision sensor network. Wireless vision sensor network is an emerging field which combines image sensor, on board computation and communication links. Compared to the traditional wireless sensor networks which operate...
In recent years the spectrum of wireless sensor network applications has grown dramatically. Sensor nodes range from very cheap nodes for control dominated applications like temperature, pressure, area and health monitoring to more powerful and sophisticated nodes used for audio and video surveillance. Implementing a low power hardware/software platform for computationally intensive applications such...
In this paper we present an example of a DISPLAY-CTRL IP component verification in an SCE-MI based emulation platform. The basic parts of this platform are some transactors. Their task is communication between the testbench written in the high level language SystemC (software side) and the IP component, placing in FPGA on an emulation board (hardware side) through an SCE-MI infrastructure. Using the...
Multi-core system and the associated software parallelization techniques have become one of the major trends of SoC design. A multi-core system with high hardware efficiency and software parallelism has the potential of achieving higher system performance and lower power consumption. This paper reveals how system performance prediction and analysis for multi-core system can be done at early design...
This paper presents a versatile heterogeneous sensor network simulator library that incorporates an online power model for real-time resource management research projects. The library integrates a well-known multi-agent simulator library Swarm, a popular sensor operating system, TinyOS, and a sensor network simulator tool called TOSSIM. The motivation of designing our library is to address difficulties...
Power electronics control algorithms are relying increasingly on digital discrete-time implementation of basic blocks for development of power electronics applications. Flexible reconfigurable blocks capable of handling these algorithms in realtime is necessary. This paper discusses the effect of hardware-software partition and hardware accelerators on performance of basic modules. It is concerned...
With the process size of microelectronics shrinking well below 90 nm, the characteristics of upsets experienced by spacecraft avionics are drastically changing; traditional hardware mitigation techniques are reaching performance limitations. A method for achieving reliability, along with the performance capabilities of new technologies, is through the use of an innovative avionics architecture which...
Due to the continuous shrinking of the transistor sizes which is strongly driven by Moore's law, reliability becomes a dominant design challenge for embedded systems. Reliability problems arise from permanent errors due to manufacturing, process variations, aging as well as soft errors. As a result, the hardware will consist of unreliable components and hence, the development of embedded systems has...
Virtual Instruments are new instrument type that combining hardware and software together. A virtual instrument system includes instrument hardware, concerned software and a computer. It can control a machine and get the operating parameter of a machine. An engine test bench was developed with VC++ basing on Virtual Instruments technology. The system can control an engine and a chassis dynamometer...
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