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Due to the proliferation of reprogrammable hardware, core designs built from modules drawn from a variety of sources execute with direct access to critical system resources. Expressing guarantees that such modules satisfy, in particular the dynamic conditions under which they release information about their unbounded streams of inputs, and automatically proving that they satisfy such guarantees, is...
In previous generations of Intel FPGAs, we employed design separation through the use of LogicLock in Cyclone IIILS and Arria V devices. In the past, this meant separation of design elements as well as designated protected design boundaries in different ‘Logic Lock’ regions. Though separated logically, these regions have the same protection and risk if the key is revealed. Today, using Partition-Based...
In this paper, three different approaches are considered for FPGA based implementations of the SHA-3 hash functions. While the performance of proposed unfolded and pipelined structures just match the state of the art, the dependencies of the structures which are folded slice-wise allow to further improve the efficiency of the existing state of the art. By solving the intra-round dependencies caused...
The Intrusion Detection Systems (IDS) is becoming important and quite timing/space consuming due to the increasing volume of explosive data flood. During the past decades, there have been plenty of studies proposing software mechanisms to exploit the temporal locality in the IDS systems. However, it requires considerable memory blocks to store the redundancy table, therefore, the performance as well...
The cryptographic hash algorithm has been developed by designers with the goal to enhance its performances in terms of frequency, throughput, power consumption and area. The cryptographic hash algorithm is implemented in many embedded systems to ensure security. It is become the default choice to ensure the information integrity in numerous applications. In this paper, we propose a pipelined architecture...
Confidential Information transactions need cryptographic algorithms to give access to data only for authenticated individuals. In the era of smart phones and internet of things, most of the data exchange occurs between small and smart electronic gadgets. Cryptographic algorithms are necessary in smart gadgets to secure the sensitive data. Hardware implementations of cryptographic protocols on ASIC/FPGA...
Physically Unclonable Functions (PUFs) based on the evaluation of uninitialized SRAM are one of the most promising PUF candidates to date. However, transferring their concept to Xilinx FPGAs is not straightforward since all SRAM-based block memories in these FPGAs are automatically cleared on power-up, destroying the desired initial bits of information. In this work we therefore propose a novel strategy...
In this paper we present the architectural design of the tiny scale very long instruction word (VLIW) soft-core processor TinyVLIW8. The processor is designed to achieve a minimal instruction execution time and design size. Although, the instruction repertoire is not large, it is dequate for control tasks, which require decision making that could not easily be implemented in an application specific...
Many electronic applications use cryptographic algorithms implemented in embedded devices to provide some form of security, e.g. smart cards (banking, SIM, access control), mobile phones, wifi routers, etc. The tight resource constraints of the devices, typically silicon area and power or energy, together with requirements from the application, typically latency or throughput, demand highly efficient...
. True-random number generators (TRNGs) are being recently defined, designed and prototyped on digital electronic circuits, like part of encryption and decryption algorithms. They provide very interesting results in terms of security and cost. In harsh environments, like aerospace applications, Single Event Upsets (SEUs) are a main concern. TRNGs are currently used in satellite communications to enhance...
TCM (Trusted Cryptography Module) is the core of national trusted computing technology. This paper proposes the extending method of TCM in the embedded system, which is implemented on ARM embedded platform. After hardware architecture of trusted computing PC platform that is defined by TCG is researched and universal external interface of embedded platform is analyzed, SPI bus is selected to extend...
Resource constraints imposed upon embedded systems make it particularly challenging to provide high levels of security assurance without degrading their performance. We present a method for increasing security assurance of embedded systems without reducing system performance. This method employs a systemic dissolution of architected resources that reduces the attack surface of embedded systems. We...
In this paper, two different FPGA implementations of the lightweight cipher PRESENT are proposed. The main design strategy for both designs is the utilization of existing RAM blocks in FPGAs for the storage of internal states, thereby reducing the slice count. In the first design, S-boxes are realized within the slices, while in the second design they are also integrated into the same RAM block used...
This paper provides the design of stream ciphers based on hash functions and an alternating step generator based on clock control. The keystream generators used for the design of stream ciphers uses low hardware and low power based circuits called Linear Feedback Shift Register circuits. The first two stream ciphers use toeplitz hash, CRC hash and keystream generation circuits whereas the third one...
Self-healing systems can restore their original functionality by use of run-time self-reconfiguration, a feature supplied by state of the art FPGA devices. Commonly, integrity checks are performed by reading back the device configuration and validating its hash value. Systems which are prone to tampering and piracy of intellectual property may disable configuration readback, which renders this method...
This paper proposes Flex Core, a hybrid processor architecture where an on-chip reconfigurable fabric (FPGA) is tightly coupled with the main processing core. Flex Core provides an efficient platform that can support a broad range of run-time monitoring and bookkeeping techniques. Unlike using custom hardware, which is more efficient but often extremely difficult and expensive to incorporate into...
Recent cryptanalysis on SHA-1 family has led the NIST to call for a public competition named SHA-3 Contest. Efficient implementations on various platforms are a criterion for ranking performance of all the candidates in this competition. It appears that most of the hardware architectures proposed for SHA-3 candidates are basic. In this paper, we focus on an optimized implementation of the Shabal candidate...
Reconfigurable technologies are getting popular as an instrument not only for verification and prototyping but also for commercial implementation of Multi-Processor System-on-Chip (MPSoC) architectures. These systems, in particular Network-on-Chip (NoC) based ones, have emerged as a design strategy to cope with increased requirements and complexity of modern applications. However, the increasing heterogeneity,...
The growing demand for secure communications has lead to the utilization of cryptographic mechanisms on-board spacecrafts. However, that it not a trivial task due to sensitivity of cryptographic primitives to bit-flips, which are commonly caused by the radiation found in space. On-board processing has mitigated single event upsets (SEUs) by employing the traditional triple modular redundancy (TMR),...
In this article a low-cost KNX-Secure system is presented. It takes advantage from the facilities that the new in-system Flash FPGAs provide: an unique code for each device (DNA) and internal One-Time-Programmable registers. The well known AES-GCM cryptographic and authentication algorithm in combination with a key generated into the FPGA is proposed for the device dependent code ciphering. The modules...
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