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UART (Universal Asynchronous Receiver Transmitter) is a kind of serial communication protocol; mostly used for short-distance, low speed, low-cost data exchange between computer and peripherals. During the actual industrial production, sometimes we do not need the full functionality of UART, but simply integrate its core part. UART includes three kernel modules which are the baud rate generator, receiver...
This paper presents the design and implementation of a complete communication system using the GMSK modulation scheme. The hardware is described in VHDL and implemented on Altera FPGA. Additionally, each block used to perform the implementation is completely described accomplishing all the requirements of this kind of modulation. Mueller & Müller algorithm is also performed to ensure timing synchronization...
PCM serial code maybe transferred without bit and byte synchronization. A PCM decoding method by self-synchronizing is given for this instance. The decoding process includes bit synchronizing using PCM serial code received, bit shifting and byte recognizing by given data frame. The VHDL is used to accomplish the method. The improved method is put forward by analyzing the possible error brought by...
In this paper the description of hardware modules for managing underwater wireless optical communication is proposed. The modules have been developed for testing purposes considering previous released protocols for optical wireless communication (i.e. IEEE 802.11-IR) and the characteristics of underwater medium and taking into account the possible integration with current technologies for terrestrial...
This paper presents FPGA implementation of various V-BLAST detection algorithms which are maximum likelihood, zero forcing and minimum mean squared error. Firstly, the MIMO V-BLAST system structure, the mathematical models and a variety of receiver detection algorithms have been studied detailedly. And then we analyze the characteristic and performance of typical algorithms and focus on using the...
In this paper, we present the design and implementation of a PLC (Power-Line Communication) Modem based on Orthogonal Frequency Division Multiplexing (OFDM). The PLC device implements OFDM in both transmitter and receiver using VHDL programming. The OFDM processor is synthesized in a Field Programmable Gate Array (FPGA) that acts as a Core Processor in the PLC Modem. Furthermore, the prototype includes...
The work mainly concentrates to create a remote controlled environment to address every device with a unique ID. To address this issue we are in need of a protocol. It is the RC5 protocol. This was to implement and demonstrate this RC5 protocol and use it to control three to four devices. We have chosen to use FPGA to process the information. In this work we implemented RC5 protocol and used this...
In order to increase transfer rate and enhance performance in mass data transmission and storage in real time system, a high performance Serial Advanced Technology Attachment generation 2(SATA II) host controller is proposed in this paper. This paper presents how to improve the hardware performance in course of implementation and validation. The controller was designed using VHDL and developed in...
Frequency offset is of the main problems in Orthogonal Frequency Division Multiplexing (OFDM) system. A frequency offset between the local oscillator at the transmitter and receiver causes frequency shift in the signal, while in time-varying channel, it can cause a spread of frequency shift known as the Doppler spread. This leads to loss in the orthogonality between subcarriers and results in intercarrier...
This paper introduces the use of combined decimal sequences in a code division multiple access (CDMA) system. It presents the design and implementation of a DS-CDMA base-band module on an FPGA. The designed transceiver employs a combined D-sequence generator as a spreader/despreader unit. The transceiver have been designed using VHDL design entry method and simulated using Mentor Graphics FPGA Adv...
A GPS receiver based on FPGA and MicroBlaze was developed. This kind of GPS receiver is made up of a RF Front- End and FPGA, with NemeriX NJ1006A and Xilinx XC2VP30 as its core chips. The RF Front-End chip NJ1006A receives the GPS signal and converts it to IF signal which is transfered to FPGA .The correlators array , C/A code generator,C/A code DCO and carrier DCO were analyzed and designed with...
A full digital intermediate frequency (IF) differential BPSK direct sequence spread spectrum receiver platform is introduced. In the receiver the FPGA chip based hardware design is adopted and digital signal processing algorithm is combined to realize signal acquisition, tracking and demodulation. A scheme of a parallel combined serial acquisition is applied, and the Tong decision algorithm is also...
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