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Overviews of comprehensive geometry-based and electrical-based PCB layout checks are given. Layout check results are then compared with signal integrity simulations at various levels: with vs. without trace couplings; with vs. without via couplings; ideal PDN vs. non-ideal PDN; partial channel vs. full channel. A DDR3 memory design is used as an example.
Current mode (CM) scheme provides suitable alternative for the high speed on-chip interconnect signaling. This paper presents a energy-delay optimization methodology for the current-mode (CM) signaling scheme. Optimization for the CM circuits for on-chip interconnects requires a joint optimization of driver and receiver device sizes, as their parameters which affect the energy-delay performance depend...
A novel methodology for accurate and efficient static timing analysis is presented in this paper. The methodology is based on finding a frequency domain model for the gates which allows uniform treatment of the gates and interconnects. It is shown that despite the highly nonlinear overall gate model, a frequency domain model of the gate with the model parameters, gate moments, as functions of the...
We performed analyses of the frequency response of cloth inductors and thin-film inductors using an amorphous core, applying both to miniature dc-dc converters. Because these inductors are used in high-frequency bands from 1 to 100 MHz, the frequency dependence of the inductance L, capacitance C and resistance R in the inductors cannot be disregarded. The undetermined coefficients in a least-squares...
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