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This paper describes the design of mm-wave integrated transformers and their application within a power amplifier (PA) in a 28 nm CMOS technology. The PA presents a 2-stage common-source differential topology and employs one transformer at the input and another at the output to perform single-ended to differential conversion, as well as another transformer to perform interstage matching. The baluns...
This paper presents novel Built In Sensor (BIS) to test a well-known analog building block; the Current Feedback Operational Amplifier (CFOA). The proposed BIS tests on the terminal characteristics of the analog block. It has no voltage degradation. Moreover, it has a simple design, very small area and can detect both short and open circuit faults. Simulations are made to test CFOA-based universal...
The paper presents a novel programmable BICS topology in IBM 65 nm CMOS technology. Programmability, which is the main motivation of this approach, is shown on three different CUTs, simultaneously. It is shown that proposed topology has 473 MHz bandwidth, 200.6ps detection time with 1.5μA sensitivity. Moreover, these specifications are achieved with only one control pin. The advantage on area overhead...
The paper presents a novel programmable Built In Current Sensor (BICS) topology in IBM 65 nm CMOS technology. Proposed topology has 2.086 GHz bandwidth and 38.9ps detection time. Moreover, a new built-in IDDQ test flow is proposed. Proposed test flow is applied to a charge pump. The results show 100% fault coverage for the defects that affects the output of the charge pump (CP). 97.87% overall fault...
A fully integrated 5.6-6.4 GHz power amplifier is implemented in a 0.25 mum SiGe-HBT technology using an on-chip transformer combining structure. The novel combiner topology combines the output power of two push pull pairs and leads to a reduced transistor size compared to a conventional combiner while enhancing the efficiency and maintaining the maximum output power. Electromagnetic modeling of the...
3D contactless technology based on capacitive coupling represents a promising solution for high-speed and low power signaling in vertically integrated chips. AC coupled interconnects do not suffer from mechanical stress, and the parasitic load is much reduced when compared to standard DC solutions, such as wire bonding and micro bumps. Communication system based on wireless interconnection scheme...
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