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A fully integrated and packaged Power Amplifier (PA) has been realized in 130nm STMicroelectronics H9SOIFEM. The PA is based on a new dedicated power cell delivering very good RF performances. At 28dBm output power, ACPR is −40dBc and PAE is 40%, reaching a FOM (ACPR+PAE) of 80 at 1.95GHz 3G standard, under 3.4V. Neither linearization nor efficiency enhancement technics have been used. The core power...
The design of an ultra-low voltage CMOS wideband LNA topology operating under a 0.6 V power supply with high gain and high IP2 is presented in this paper. The circuit performance is targeted towards use in direct conversion receivers, where a high IP2 is required. The LNA operates in sub-1 GHz applications reaching frequencies as low as 50 MHz, as it is required by IEEE 802.22 standard. The topology...
Semi-custom design flows are a key factor for the rapid growth of integrated circuits and systems. They lower design complexity through the use of pre-designed and pre-characterized functional components called standard cells, instead of assuming that designers have to draw, place and connect each transistor. In this way, modeling of complex systems is easier. As CMOS technologies evolve into deep...
Since the early 1990's, electrical energy tends to replace pneumatic and hydraulic energy aboard aircrafts. This is lead by MEA project and allows to reduce weight and volume of the actuators. But an increase of onboard electric energy leads to EMI issues. To comply with EMC standards, an EMI filter is often added to the electrical systems. In order to reduce the weight and volume impact of EMI filters,...
In this paper we study the information rates, bit energy and noise efficiency factor (NEF) of three simple amplifier topologies: the common source amplifier, self biased transconductor and the simple operational transconductance amplifier (OTA). The calculated information rates, bit energy and NEF are determined by experimentally based estimates of input referred noise. The self biased transconductor...
The present paper addresses an improved low-power high-speed buffer amplifier topology for large-size liquid crystal display applications. The proposed buffer achieves high-speed driving performance while drawing a low quiescent current during static operation. The circuit offers enhanced slewing capabilities with a limited power consumption by exploiting a slew detector which monitors the output...
This paper proposes and develops two simple efficient techniques for optimizing the closed-loop transient response of three-stage amplifiers for large capacitive load applications. The proposed approaches exploit a current comparator in the inner amplifier nodes to sense the input voltage transients and switch on an auxiliary driving device providing slew-rate enhancement and settling time improvement...
This paper describes a design flow for the circuit-level optimization of a technology. The concurrent exploration of device characteristics and library design choices leads to a more application-optimal technology. We illustrate the design flow by: 1) analyzing the impact of buffer cell design, and 2) by optimizing a 130 nm technology for low operational power.
This paper describes a comparative analysis between two topologies of operational amplifiers to design a 40 MS/s 12-bit pipeline analog to digital converter (ADC). The analysis includes AC and transient simulation to select the proper topology. This ADC is implemented in a 0.35 mum AMS CMOS technology with 3.3 V single power supply. The capacitors and selected operational amplifiers were scaled for...
The next generation of wireless communication is a ubiquitous radio system concept, providing wireless access from short-range to wide-area, with one single reconfigurable and adaptive system for all envisaged radio environments. This paper presents the design approach of RCO (reconfigurable concurrent oscillator) that simultaneously generates two or more signals of different frequencies that eliminate...
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