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Leakage power is a key challenge in VLSI design, and process variations have aggravated the problem. Interconnects have become very critical in modern VLSI designs and have started to play a major role in determining the power and performance of a design. Certain VLSI circuits such as FPGAs are interconnect dominated, such that their performance and power are largely governed by the interconnects...
Unlike CMOS circuit design, even though there are promising advantages to use carbon nanotubes for digital circuits in terms of power, delay, temperature, and area, one of the critical issues to design by using carbon nanotubes is optimization of additional design parameters such as number of nanotubes and pitch size. To reduce the optimization complexity of the increased technology parameters, in...
With the CMOS transistors being scaled to sub 45 nm and lower, Negative Bias Temperature Instability (NBTI) has become a major concern due to its impact on PMOS transistor aging process and the corresponding reduction in the long-term reliability of CMOS circuits. This paper investigates the effect of NBTI phenomenon on the setup and hold times of flip-flops. First, it is shown that NBTI tightens...
FinFETs with channel surface along the <110> plane can be easily fabricated by rotating the fins by 45?? from the <100> plane. By designing logic gates, which have pFinFETs in the <110> plane and nFinFETs in the <100> plane, the gate delay can be reduced by as much as 14%, compared to the conventional <100> logic gates. The reduction in delay can be traded off for reduced...
As the microprocessor speed increases from 500MHz to 1GHz and beyond, SOC designers are forced to innovate new schemes in their use of cache memory for high speed access. In this paper, clock to wordline path delay is optimized using a novel circuit design technique. Using this novel circuit, clock to word line path delay is optimized by 2.5 times at worst case corner. For a typical memory instance...
Due to the intrinsic difference between fan-in and fan-out counts of a retimed component, the number of flip-flops tends to be undesirably increased in a conventional retiming procedure, which can cause a significant area/power penalty on the retimed circuit. Nonetheless, because of the higher dominance on interconnect delays, without a mechanism to reflect real physical design accurately, the clock...
In high-frequency microprocessor design, placement plays a significantly different role from that in large ASICs. Not only does it have to find a good global placement solution, placement needs tighter interaction with physical optimizations to improve every picosecond possible. This paper will introduce practical placement techniques that integrate buffering and gate sizing to maximize timing improvement...
This paper describes a timing-driven optimization technique for the synthesis of multi-level logic circuits. Motivated by the parallel prefix problem, the proposed timing-driven optimization produces logic circuits with ldquolookaheadrdquo properties due to the inherent parallelism among the synthesized sub-circuits. Lookahead logic circuits are synthesized using global critical path sensitization...
The reliability against transient faults poses a significant challenge due to technology scaling trends. Several circuit optimization techniques have been proposed in the literature for preventing soft errors in logic circuits. However, most approaches do not incorporate the effects of other design metrics like delay and power while optimizing the circuit for soft error protection. In this work, we...
During synthesis of circuits for Boolean functions area, delay and testability are optimization goals that often contradict each other. Multi-level circuits are often quite small while circuits with low depth are often larger regarding the area requirements. A different optimization goal is good testability which can usually only be achieved by additional hardware overhead. In this paper we propose...
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