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This paper presents a method to model the drain current of LDMOS working in the 3rd quadrant (Vds<0), which is important for power management IC design. The DIBL effect in 3rd quadrant is shown to be much more significant than that in 1st quadrant (Vds>0), and is not captured by the existing LDMOS models. Also, the threshold voltage model is not accurate in 3rd quadrant, where the drain-body...
This paper discusses the design of a 60 GHz low noise amplifier (LNA) using a standard low power SOI CMOS process from ST Microelectronics. First, we outline the technology as well as the mm-wave design challenges. Using recent work on coplanar waveguide (CPW) modeling, we describe how it's possible to use parametric, 3D electromagnetic simulation to complete or replace analytical models of on-chip...
Current mode (CM) scheme provides suitable alternative for the high speed on-chip interconnect signaling. This paper presents a energy-delay optimization methodology for the current-mode (CM) signaling scheme. Optimization for the CM circuits for on-chip interconnects requires a joint optimization of driver and receiver device sizes, as their parameters which affect the energy-delay performance depend...
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