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Circuits employing advanced performance and power management techniques (clock gating, half-cycle paths) are found to be much more sensitive to NBTI primarily due to differential and asymmetric aging, with a 1% transistor drift leading to as much as 3% circuit drift in some cases. For the first time, we report a monotonic reduction in variance of the log parameters (Ln(ΔF/F) and Ln(ΔID/ID)) as a function...
A feasible computational framework that enables improved predictability of NBTI degradation within commercially available tools is discussed. The NBTI model is used for both delay correction in transistor characterization data and real-time circuit operation where recovery is present. The complementary nature of implementation is readily incorporated into existing model extraction and verification...
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