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This paper presents a model order reduction technique based on balancing-free square root (BSR) method for high speed coupled integrated circuit interconnects. The salient features of this technique are the less CPU time resulting from the passivity of the reduced transfer function, and the availability of provable weighted error bounds for the reduced-order system. This paper also shows that the...
The control-to-output and the duty ratio-to-inductor current transfer functions of peak current-mode controlled PWM dc-dc buck converter in CCM are derived and illustrated. The closed inner-current loop and the power stage inductor current-to-output voltage transfer functions are used to derive the control-to-output transfer function of the peak current-mode controlled buck converter in CCM, which...
A novel methodology for accurate and efficient static timing analysis is presented in this paper. The methodology is based on finding a frequency domain model for the gates which allows uniform treatment of the gates and interconnects. It is shown that despite the highly nonlinear overall gate model, a frequency domain model of the gate with the model parameters, gate moments, as functions of the...
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