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Hybrid integration has been employed for most of the current market available silicon photonics. A novel modular packaging scheme, MEPIC-iMEP3, is proposed for rapid development and high flexibility. One of the critical modules in this packaging scheme is the multichip integration onto the i-MEP3 substrate for sub-micron accuracy. In this study, a series of specially designed test chips and test substrate...
This paper reports a polarization switching antenna integrated with RF MEMS switches based on the novel packaging platform using silicon-on-quartz (SoQ) substrate and BCB(benzocyclobutene) bonding technique. By using the SoQ wafer as an antenna substrate as well as for a packaging lid, fabrication complexity and degradation of RF performances of the antenna due to the parasitic effects coming from...
Most MEMS microphone systems on the market are packaged by conventional chip bonding and wire bonding.. A significant step towards miniaturization was achieved earlier by applying flip-chip bonding to MEMS microphone packaging. This technology is called chip scale MEMS package (CSMP). Thereby the package size could be reduced to 2.8 ?? 2.05 ?? 0.9 mm3 compared to a standard size of 3.76 ?? 2.95 ??...
Due to the environmental protection issues and regulations, a lot of electronic material suppliers try to search for the replacement materials which include the lead-free solder joints and the anisotropic conductive films (ACFs). ACF is widely used in high quality, excellent signal interconnection and fine pitch products. Nevertheless, during the fast flow and curing process of the electronic material,...
In this paper we present the results of initial studies of a new dry film polymer, PerMX developed by Du Pont for wafer level packaging applications. PerMX is a high resolution permanent photosensitive dry film material with low temperature processing capability. Dry film is easy to deposit on large wafers compared to the liquid form materials. We have carried out initial chip scale characterization...
Today, flip chip technology is a main stream of interconnection in microelectronic packaging and market forces continue to drive toward finer pitch interconnections. In this paper, fine pitch flip chip (FPFC) interconnection technology (i.e., less than 60 mum pitch) will be described. Two types of 50 mum pitch bump (Au stud & Cu pillar) will be evaluated and two different flip-chip (FC) bonding...
A method of chemical flip-chip bonding by electroless deposition process was proposed. This method positively utilizes preferential bridge deposition between metal pads in electroless Ni-B deposition and enables bump-less interconnect without loading and/or heating at lower temperature (60degC). Details of the deposition behavior for interconnection were investigated using fundamental test chips....
3D die stacking is a key technology for enabling 3D integration wherein two or more dies are stacked on top of each other with vertical interconnections. This result in high speed interconnects with reduced noise and crosstalk as compared to wire bonded assemblies. 3D integration may require sequential stacking of multiple dies without disturbing the previously bonded die. This can be achieved by...
In this study, bottom-up electroplating is used for TSV (Through Silicon via) fabrication. With the metal temporarily bonding technology, we could remove the handling substrate and perform the chip stacking process. The TSVs made by bottom-up electroplating do not need the expensive MOCVD seed layer deposition and special designed electroplater/solution. Moreover, it is independent with the DRIE angle...
A chemical flip-chip bonding method by electroless plating process has been developed. This method positively utilizes so-called "bridge" phenomenon between metal pads in electroless Ni-B plating, and enables bump-less interconnect without loading and/or heating at lower temperature (60??C). The interconnect behavior was examined using test chips and substrates with various pad-to-pad configurations...
Multi-stack anodic bonding using two electrodes is realized in this paper. The process includes two bonding steps separated by one electrodes reversal. When pre-cleaned substrates of silicon and glass are piled up and heated to predetermined temperature, voltage applied between the top and bottom substrates for bonding the first interface, when this bonding process is finished, the substrates are...
New types of packaging technology which include the wire bond and flip chip for chip scale package, demand a high wiring density, high I/O density and a high performance, which in turn, narrows the pitch of the substrate so as to achieve the smallest possible package in order to keep up with the trend of the demand for smaller, lighter, and thinner compacted consumer products. This paper discusses...
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