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In this paper, we base on data computing blocks (DCBs) and DCT watchdog technology to implement VLIW watchdog processor. 32-bit final DCT signature (F-DCT-S) and several 5-bit relay DCT signatures (R-DCT-S) will be computed by DCT watchdog scheme. These generated signatures are embedded into the instruction memory and then used to do the run time error checking. We use VLIW processor to simulation...
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