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This paper develops pipeline architecture of particle swarm optimization with random time-varying inertia weight and acceleration coefficients (PSO-RTVIWAC) based on existing serial architecture. The proposed architecture incorporated two features to reduce calculation error and keep high speed calculation with acceptable chip area cost. First, actual hardware design is simplified. Then the pipeline...
This paper presents a hardware based approach to simulate action potential of large numbers of somas within a biological neural network. At the proposed method multiple processors can work in parallel to increase processing power as required. The high speed pipelined architecture for each processor provides the computation speed of one soma per clock ratio and with multiple processors higher speeds...
As processor performance continues to outgrow memory capacity and bandwidth, system and application performance has become constrained by the memory subsystem. Promising new technologies like Phase Change Memory (PCM) and Flash have emerged which may add capacity at a cost cheaper than conventional DRAM, but at the cost of added latency and poor endurance. It is likely that systems leveraging these...
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