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In this paper, a novel VLSI architecture for one dimensional Walsh-Hadamard transform (WHT) is proposed. The core of the architecture is the HVMA (Hadamard Vector Merging Adder) that adds the products of input data words and transform (Hadamard) matrix elements in parallel using a (4:2) compressor based carry-save tree structure. The core also exploits the Hadamard matrix's property of equal distribution...
In this manuscript, we describe a fully pipelined single chip architecture for implementing a new simultaneous image compression and encryption method suitable for real-time applications. The proposed method exploits the DCT properties to achieve the compression and the encryption simultaneously. First, to realize the compression, 8-point DCT applied to several images are done. Second, contrary to...
Digital halftoning plays a central role in getting more observable grey-levels for either the innovative electronic paper or other less level devices. The hardware implementation of digital halftoning is, however, seldom fully explored. In this paper, we propose a novel implementation of digital halftoning by means of error diffusion. The proposed scheme not only can perform a new method called chaotic...
In this paper, we describe an approach for real-time detection of rotated patterns in an image using FPGA. In many approaches, a two-dimensional pattern and the target regions in the image are transformed to one-dimensional arrays or several pattern specific values which are invariant to rotation, and the regions in which the pattern may exist are listed up using them. These approaches make it possible...
This paper presents a new architecture for high performance intra prediction in H.264/AVC video coding standard, which can support H.264 high profile features. Our goal is to design an Intra prediction engine for Ultra High Definition (UHD) Decoder (4 K x 2 K @ 60 fps). The proposed architecture can achieve very stable throughput, which can process any H.264 intra prediction modes within 66 cycles...
In order to satisfy the special demand for image display in TFT-LCD, this paper presents a synthesis design and its implementation for image processing in TCON of TFT-LCD. The modules, including contrast adjustment, luminance adjustment, gamma correction and dithering technique, are designed to deal with the zoomed image, and at the same time, match the real-time requirements. All the modules are...
For performance enhancement, reconfigurable processors have to overcome the overheads of reconfigurations such as the complexity of the interconnection network and reconfiguration time. In processors dealing with multimedia applications these overheads can be reduced by providing the reconfigurability inside the processing units rather than at interconnection level. Due to the low precision data nature...
Window-based operations such as two dimensional (2-D) convolution operations are commonly used in image and video processing applications. In this paper, a new design technique that considers the neighboring pixels within the window to detect and eliminate redundant or unnecessary computations for power reduction is presented. A novel on-chip detection technique is developed for the proposed neighborhood...
Current run-time reconfigurable systems present high reconfiguration times. This is a high overhead which deeply reduce these systems' performance, and it is critical when the application has tight performance requirements. Multi-level reconfiguration (MLR) model is a good strategy to reduce the size of configuration bitstreams, reducing reconfiguration times. In this paper, a two-level reconfigurable...
This paper describes a resource-efficient vision system for the mini-robot “Khepera”. It is implemented to perform a fundamental approach of robotic navigation, which is obstacle detection by using an optical flow algorithm. This is inspired by visual perception of insects. The optical flow field is evaluated by implementing the sum of absolute differences (SAD) operation of block matching while the...
Two dimentional (2-D) convolver is a basic processing unit used in real time video and image processing algorithms. VLSI chip area and external memory bus bandwidth are two major concerns of efficient and fast 2-D convolver. Till now people have considered both of these parameters separately. Achieving low complexity and high packing density at the same time is a difficult task. This paper proposes...
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