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Several regular parallel trees have been proposed over the years to optimize logic depth, area, fan-out and interconnect count for logic circuits. In this paper, we propose a comparative study of different parallel prefix trees used in the design of a new end-around carry (EAC) adder targeting FPGA technology. This new adder is based on the fast 128-bit binary floating-point EAC adder which has been...
FPGAs are increasingly being used to design high-end computationally intense microprocessors capable of implementing floating-point operations based hardware accelerators. In this paper, the throughput was improved by increasing the number of pipelining stages of the floating-point adder, and the feasibility of advancing the system clock rate was researched by making the most of plenty of flip-flops...
Reconfigurable circuits now have a capacity that allows them to be used as floating-point accelerators. They offer massive parallelism, but also the opportunity to design optimised floating-point hardware operators not available in microprocessors. Multiplication by a constant is an important example of such an operator. This article presents an architecture generator for the correctly rounded multiplication...
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