The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
In this brief, we propose a method to design efficient adder-based converters for the four-moduli set with odd, which provides a dynamic range of bits for the residue number system (RNS). This method hierarchically applies the mixed radix approach to balanced pairs of residues in two levels. With the proposed method, only simple binary and modulo ...
Floating point multiplication is a crucial and useful arithmetic operation for many scientific and signal processing applications. High precision requirements of many applications lead to the incorporation of quadruple precision (QP) arithmetics. The logic complexity and performance overhead of quadruple precision arithmetic are quite large. This paper has focused on one of the quadruple precision...
In order to select a new Standard Hash Algorithm (SHA-3) which supplies more security, a public competition was organized by NIST in 2007. Up to now, 14 candidates have passed the 2nd round. In this paper, we focus on two of these candidate algorithms, namely BLAKE and Shabal. We present the common structure for all the SHA3 candidates. We also design the VLSI circuit and give the hardware evaluations...
BLAKE, one of SHA-3 candidates, and LAKE hash functions show the characteristic that the block length of the internal state is double its initial and final states, which means more registers are required for the implementation of the hash functions. In this paper, we explore shift register based compact hardware architectures for the two hash functions. This includes the 32-, 64-, and 128-bit datapath...
Decimal multiplication is an integral part of financial, commercial, and internet-based computations. This paper presents a novel double digit decimal multiplication (DDDM) technique that offers low latency and high throughput. This design performs two digit multiplications simultaneously in one clock cycle. Double digit fixed point decimal multipliers for 7digit, 16 digit and 34 digit are simulated...
This paper presents a direct method of reducing convolution processing time using hardware computing and implementations of discrete linear convolution of two finite length sequences (NXN). This implementation method is realized by simplifying the convolution building blocks. The purpose of this research is to prove the feasibility of an application specific integrated circuit (ASIC) that performs...
Most field programmable gate array (FPGA) devices have a special fast carry propagation logic intended to optimize addition operations. The redundant adders do not easily fit into this specialized carry-logic and, consequently, they require double hardware resources than carry propagate adders, while showing a similar delay for small size operands. Therefore, carry-save adders are not usually implemented...
The sum of absolute differences (SAD) is a distance metric commonly used to determine the similarity between two data sets. A very recent method for directly comparing the magnitude of two numbers represented in residue number systems (RNS) leads to the possibility of using modular arithmetic to compute the SAD. In this paper we propose an efficient hardware SAD unit that computes this Manhattan distance...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.