The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
The susceptibility to Single Event Upset (SEU) is very high for Configuration memory of SRAM based Field Programmable Gate Arrays (FPGA) compared to other FPGA resources. The reduction in feature sizes and core voltages leads to a reduction in the critical charge required to change the state of a memory cell. The SEUs cause failures in the system functionality implemented in FPGA. Fault tolerant techniques...
Over the last decade, several Fault-Tolerant techniques for FPGAs were proposed especially for recovering from permanent faults. Most of those techniques were based on relocation of the defective module into a new location acting as a spare. Accordingly, what is the suitable number of spares that should be added to a system? In this paper, a performability model is developed to quantitatively investigate...
The current ATLAS Tile Calorimeter read-out system is scheduled for replacement around 2023 due to old age and higher performance needs. The new proposed system is designed to be radiation tolerant, modular, redundant and reconfigurable. To achieve full detector read-out, Kintex-7 FPGAs from Xilinx will be used, in addition to multiple 10 Gb/s optical read-out links. During 2015/2016, a hybrid demonstrator...
Scaling trends of reconfigurable hardware (RH) and their design flexibility have proliferated their use in dependability-critical embedded applications. Although their reconfigurability can enable significant fault tolerance, due to the complexity of execution time in their design flow, in-field reconfigurability can be infeasible and thus limit such potential. This need is addressed by developing...
Cyber-Physical Systems need to handle increasingly complex tasks, which additionally, may have variable operating conditions over time. Therefore, dynamic resource management to adapt the system to different needs is required. In this paper, a new bus-based architecture, called ARTICo3, which by means of Dynamic Partial Reconfiguration, allows the replication of hardware tasks to support module redundancy,...
Reliability is one of the key issues in space applications. Although highly flexible and generally less expensive than predominantly used ASICs, SRAM-based FPGAs are very susceptible to radiation effects. Hence, various fault tolerant techniques have to be applied in order to handle faults and protect the design. This paper presents a reconfigurable on-board processor capable of run-time adaptation...
This paper investigates the ability to provide improved Reliability of TMR systems at comparable area and time cost using design diversity. Namely, we evaluate multiple implementations of the same functional design using a repository of methods: Templates, Case-Based, Inverted-Output, and NAND/NOR-Based methods. The design methods are tested on multiple benchmark circuits in different TMR setups for...
Field Programmable Gate Arrays (FPGA) offer many advantages to the designers of systems including high predictability in terms of resource usage and the ability to process certain (parallel) functions and data streams efficiently and quickly. To date an impediment against the use of FPGA in safety critical domains is a lack of appropriate fault tolerance techniques. This has resulted in them being...
Emerging devices open the way to build nanoscale logic cells, dedicated to high-density reconfigurable computation. Nevertheless, in an architectural context, fine-grain logic cells integration is limited by traditional interconnection scheme and associated overload. This paper describes an interconnection scheme, based on static and incomplete interconnection topologies. We also propose a method...
This paper presents a PCI-Express based platform for the analysis and evaluation of designs that combines Triple Modular Redundancy and Dynamic Reconfiguration to provide Fault Tolerance and Self-repairing capabilities. The paper presents the general architecture of the platform and exemplifies its functionality with the implementation of a Self-Repairing CAN Gateway.
FPGAs are applicable to implementation of fault tolerant systems due to their reconfigurability. Such fault tolerant systems can be classified according to recovering methods: fail-soft and standby-redundant systems. In this work, we propose a probabilistic model for both FPGA-based fault tolerant systems, and analyze the reliability and performance of the systems. Analytical results show that there...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.