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In wireless communication system, power saving mechanism is a key issue since a mobile station operates depending on limited power. Hence, the IEEE 802.16e system provides three types of power saving classes (PSC I, PSC II and PSC III) for the mobile station (MS) to reduce power consumption. Many models have been made to analyze the performance of power saving mechanism (PSM) of the IEEE 802.16e system...
This paper presents the new design of a CMOS current comparator for high speed and minimum size. This enables a very low response time to achieve high speed and less circuit complexity. In addition we have got less power consumption. A new current comparator exhibits high speed whilst maintaining low power consumption. Simulation results allow the design approach to be validated with performance comparison...
In the majority of the Digital signal processing (DSP) applications, the critical operations usually involve many multiplications and /or accumulations. So, for real time signal processing applications, high throughput multiplier -accumulator (MAC) is always a key element to achieve a high-performance digital signal processing application. In the last few years, the main consideration of MAC design...
The use of multiple voltage domains in an integrated circuit has been widely utilized with the aim of finding a tradeoff between power saving and performance. Level shifters allow for effective interfacing between voltage domains supplied by different voltage levels. In this paper we present a low power level shifters in the 90 nm technology node capable of converting subthreshold voltage signals...
Static random access memories (SRAMs) comprise an increasingly large portion of modern very large scale integrated (VLSI) circuits. The increasing importance of embedded SRAM is due to its low circuit activity factor, leading to low active power density, and productivity of design. The power consumption has become an important issue and has lead to the development of numerous schemes aimed at limiting...
In this paper we examine a quasi static and a static ultra low-voltage precharge CMOS logic. The static ultra low-voltage logic can be used to design high speed and energy efficient CMOS circuits. Using the proposed circuit technique the static current consumption can controlled and the logic style is suitable for large logic depth, i.e. serial adders. The delay of a static ultra low-voltage gate...
Due to the importance of power/ground network, lots of researches have been made on it. But they only focused on the minimal area of it. By discussion on the relation among Vdd, performance and power consumption, this paper proposes an optimal algorithm using GA and SLP method where area, performance and power consumption can be simultaneously evaluated. As a result, the power/ground network is designed...
We propose a high-resolution 8-bit time-to-digital converter that uses two-level fractional difference conversion to reduce area and power consumption. Two delay-locked loops stabilize the propagation delay in the upper and lower buffer chains of the Vernier delay line that is used to make the measurement. In a transistor-level simulation using 0.35 ??m technology, this architecture achieves a resolution...
Enhancing interconnect robustness against variations is crucial to system performance and reliability in sub-65 nm technologies. We present a new interconnect design methodology to optimize power consumption and robustness during buffer insertion. Using closed form expressions for interconnect delay and delay variation, we construct a design space for the interconnect. Through power-robustness tradeoff...
In this paper a new full adder (FA) circuit optimized for ultra low power operation is proposed. The circuit is based on modified XOR gates operated in the subthreshold region to minimize the power consumption. Simulated results using 65 nm standarad CMOS models are provided. The simulation results show a 5%-20% for frequency ranges from 1 KHz to 20 MHz and supply voltages lower than 0.3 V.
In this paper a new approach for skew compensation in energy recovery clock distribution networks is introduced by manipulating the operating speed of the flip-flops. Three types of flip-flops: ??fast??, ??standard??, and ??slow?? are used. Distributing flip-flops according to their delay requirements would reduce the effect of the clock's skew on the outputs of sequentially adjacent flip-flops. This...
Wireless ad hoc networks consist of nodes which can communicate with each other in a peer-to-peer fashion over single hop or multi hops without any fixed infrastructure such as access point or base station. In flat topology there is no topology management concept and all the nodes participate in routing. In this paper the task of topology management for ad hoc networks is implemented using routing...
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