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Large-scale Atomic/Molecular Massively Parallel Simulator (LAMMPS) code was examined in an Intel Quad-Core Xeon platform for its speedup and scaling ability. The study shows that the most time-consuming task in the code is force computing and this part can be scaled linearly. However, other tasks do not have this feature. Future work will focus on speeding up of these other parts to enhance the performance...
Branch prediction is an important topic in modern computer architecture research. Predictors attempt to improve the performance of a processor with a reasonable hardware cost. In the last decade, many prediction schemes have been developed in order to achieve this objective, each of them with different cost/performance tradeoffs. Identifying the optimal predictor for a given architecture and set of...
The arrival of multi-core chips has heightened interest in the discipline of parallel programming, a topic that has received much attention for many years. Computer architects have much to learn from sound principles for structuring software and expressing parallel computation. This talk will cover principles for the design of computer systems to support composable parallel software - the idea that...
The very long instruction word (VLIW) architecture is considered to be one of the promising methods of increasing performance beyond standard reduced instruction set computing (RISC) architectures. However, few generally-accepted VLIW simulation environments are available for us in exploring the VLIW instruction set architectures (ISA) and their corresponding microarchitectures. Motivated by characterizing...
Performance evaluation techniques for fundamental graphics algorithms and for algorithms to be used in multimedia and embedded systems are investigated. Models of computation considering only arithmetic and logic operations taken on input data are regarded as inadequate for processors with instruction-level parallelism. For experimental evaluation of graphics algorithms clock-cycle counting is found...
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