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Scalable High efficiency Video Coding (SHVC) is the scalable extension of the latest video coding standard High Efficiency Video Coding (HEVC). One of the key novelties introduced by SHVC is that it enables hybrid codec scalability. This basically means that the video layers can be encoded with different video standards providing backward compatibility between codecs. In this paper, we propose a software...
This paper proposes a decoder-side intra mode derivation algorithm for block-based video coding. Instead of explicitly coding intra mode, the algorithm derives intra mode at both encoder and decoder using a template-based method. Based on rate-distortion optimization, the encoder locally determines whether intra mode derivation or intra mode explicit coding is used. Further, as no intra mode is coded,...
The High Efficiency Video Coding (HEVC) in-loop filtering is designed to reduce coding artifacts caused by image transforms and quantizations. HEVC in-loop filtering is divided to the deblocking filter and the sample adaptive offset filter, and these two filters take about 20% of total decoding time. This paper presents a very low-power (39 mW) programmable coprocessor architecture to HEVC in-loop...
Depth maps are made up of sharp edges and near homogenous areas. To better represent object edges in depth videos, the three-dimensional (3D) extension of the High Efficiency Video Coding (HEVC) standard allows the use of additional Depth Modeling Modes (DMM) to the existing intra-prediction modes. One of these modes, Mode 3, performs distortion calculations on a set of pre-defined Wedgelet lists...
Video coding standards (e.g. H.264, HEVC) use slice, consisting of a header and payload video data, as an independent coding unit for low latency encode-decode and better transmission error resiliency. In typical video streams, decoding the slice header is quite simple that can be done on standard embedded RISC processor architectures. However, universal decoding scenarios require handling worst case...
In this paper, an application-specific instruction-set processor (ASIP) implementation for interpolation operation for high efficiency video coding (HEVC) decoders is proposed. HEVC is a new video compression standard that has higher compression efficiency than the previous ones. The proposed ASIP is implemented on the XRC_D2MR processor by augmenting the instruction set architecture in Xtensa Tensilica...
The complexity of high performance digital systems has rapidly increased. When we design such systems in a system-on-chip (SoC), lots of predesigned intellectual properties (IPs) are integrated to build a system. To verify the functionality of such systems, conventional simulation methods take extremely long time and they have limited debugging capability due to the existence of many predesigned IPs...
Conventional mixed-resolution (MR) stereoscopic video where one view has full resolution (FR) and the other view has a lower resolution has shown to provide similar subjective quality compared to symmetric FR stereoscopic video while decreasing the encoding complexity considerably. In this paper, we propose a new cross-asymmetric mixed-resolution scheme where both views have a lower resolution compared...
With recent advances in computing and communication technologies, ubiquitous access to high quality multimedia content such as high definition video using smart phones, Net books, or tablets is a fact of our daily life. However, power is still a major concern for any mobile device, and requires optimization of power consumption using a power model for each multimedia application, such as a video decoder...
This paper presents a design methodology for hardware/software (HW/SW) architecture design using ESL tools (Electronic System Level). From C++ descriptions, our design flow is able to generate hardware blocks running with a software part and all necessary codes to prototype the HW/SW system on Xilinx FPGAs. Therefore we use assistance of high level synthesis tools (Catapult C Synthesis), logic synthesis...
The design of embedded systems is often subject to strict requirements concerning various aspects, including real-time performance, power consumption and die area. For mobile devices especially, power consumption is often the most important issue. In order to meet these requirements an adequate system architecture needs to be designed and the embedded software needs to be optimized. For complex applications,...
MPEG Reconfigurable Video Coding project aims at providing more flexible and easier solutions to specify video coders and decoders. Many contributions are devoted to the RVC-CAL language, the standard description language. There are also contributions about the general framework of this new model of video coding, and many CAL descriptions for video algorithms. However, RVC compliant implementations...
The Reconfigurable Video Coding (RVC) framework is a recent ISO standard aiming at providing a unified specification of MPEG video technology in the form of a library of components. The word “reconfigurable” evokes run-time instantiation of different decoders starting from an on-the-fly analysis of the input bitstream. In this paper we move a first step towards the definition of systematic procedures...
This paper analyzes the reasons of asynchronous between audio and video image for current 3G video phones. A solution for improving the synchronization between audio and video data is proposed. The solution proposed in this work mainly consists of software components, according to which hardware needs to be selected. It also gives the video phone terminal structure, block diagram for H.324M video...
H.264 has become a popular video compression standard for years; however, the complexity of computation and huge amount of external data access are still the main problems. In this paper, we will propose two mechanisms to fulfill high performance H.264 baseline profile decoder on PAC Duo SOC platform. To reduce the complexity of computation, in addition to algorithm optimization, we use parallelizing...
In this paper motion compensation IP core design based on SOPC technology is researched, which achieves the software hardware co-design method in video decoding to overcome the drawbacks of the software decoding and hardware decoding. The design of hardware modularization which is based on the motion compensation algorithm in MPEG-4 video decoding standard is completed by using verilog HDL language...
The computational complexity of H.264 video coding standard is two or three times higher than that of H.263 and MPEG-4. Especially, the operations of the entropy coding and deblocking filter are the most complex parts in the decoder. In order to reduce the computational complexity of these operations, we propose a fast algorithm for H.264 decoder implementation, which containing a group-based CAVLC...
Design at the Electronic System-Level (ESL) tackles the increasing complexity of embedded systems by raising the level of abstraction in system specification and modeling. Aiming at an automated top-down synthesis flow, effective ESL design frameworks are needed in transforming and refining the highlevel design models until a satisfactory multi-processor system-on-chip (MPSoC) implementation is reached...
The elaboration of new and innovative systems such as MPSoC (Multiprocessor System on Chip) which are made up of multiple processors, memories and IPs lies on the designers to achieve a complex codesign work. Specific tools and methods are needed to cope with the increasing complexity of both algorithms and platforms. Our approach to design such systems is based on the usage of a high level of abstraction...
A System-on-Chip Design of VLD (Variable Length Decoder) in multi-standard video decoder is proposed in this paper. Our design supports all the popular video compression standards, e.g. MPEG-1, MPEG-2, MPEG-4, H.264, AVS, RealVideo. Benefit from its low power, the design is especially suitable for wearable multimedia applications. Simulation results show that the whole design takes an area of 1.04mm2,...
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