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The trade-off between speed and power consumption has become a critical concern as process technology make in-roads to 40nm proximity in modern VLSI technology. We can reduce this trade-off by compensating with accuracy i.e. if an application like Digital signal processing (DSP) can accept some errors then a large power can be saved and at the same time speed can be enhanced. In this paper, we propose...
The present title discloses novel concept for high speed computing using essentials of Ancient Indian Vedic Mathematics, modified and implemented using VLSI-FPGA architecture for best performance. The proposed architecture aims to define highly optimized multiplier unit which allows the highly intensive units of Signal Processing, Image Processing, Data Encryption/ Decryption and most other techniques...
This paper comprises of new low power multiplication algorithm and VLSI architecture. The one less than previous is foundation to built the proposed algorithm. The algorithm is simple straightforward to find NxN unsigned binary number multiplication using 2n-1 constant number which is used recursively for both multiplicand and multiplier. It revealed that reusability of the hardware resource results...
Efficient modular adders and subtractors for arbitrary moduli are key booster of computational speed for high-cardinality Residue Number Systems as they rely on arbitrary moduli set to expand the dynamic range. This paper proposes a new unified modular adder/subtractor that possesses a regular structure for any modulus. Compared to the latest modular adder/subtractor, which works for modulus in the...
No Trouble Found (NTF) has been discussed for several years [1]. An NTF occurs when a device fails at the board/system level and that failure cannot be confirm by the component supplier. There are several explanations for why NTFs occur, including: device complexity; inability to create system level hardware/software transactions which uncover hard to find defects; different environments during testing...
In this work, fast binary to binary-coded-decimal (BCD) code converters for decimal communications are proposed. By employing new recoding circuits, our proposed converters can perform fast and area-efficient conversions from binary inputs to decimal outputs to speed up decimal multiplications. Synthesis results show that our proposed converters can achieve over 60% delay with slight area increase...
Area, Speed and power are the basic design constraints which affects the performance of VLSI circuits. The main hurdle in the VLSI implementation of digital circuits is that either the design can be area efficient or power efficient or speed efficient, but not all area-time-speed efficient simultaneously. Optimizing one parameter affects the other. In this paper, an optimal multi-objective approach...
In this paper, we have proposed high-speed binary to binary-coded-decimal (BCD) converters for decimal multiplications. By employing new recoding methods, our proposed converters can perform high-speed conversions from binary numbers to decimal outputs. Synthesis results show that our proposed converters can achieve over 66% delay and 0.8% area reduction compared with previous proposed method, respectively...
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